Using ACFs Generated by FPGA Express Software
With FPGA Express software, you can either generate a new Assignment & Configuration File (.acf), along with an EDIF netlist file (.edf) and Library Mapping File (.lmf), to be imported into the MAX+PLUS® II software, or you can place a copy of an existing ACF in the FPGA Express output directory. If you use an existing ACF, FPGA Express updates the ACF with additional information, such as the global project synthesis style, as it processes the design. Each line in the ACF that is modified by the FPGA Express software is marked with a {synopsys} comment at the end. You should then place this ACF in the MAX+PLUS II project directory.
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If an existing ACF has been modified by FPGA Express, then processed by the MAX+PLUS II Compiler, the resulting ACF may specify an incorrect LMF. If so, the MAX+PLUS II software displays the error message Can't find design file <cell name>. You can correct this error in MAX+PLUS II software by specifying the FPGA Express-generated <project name>.lmf file in the LMF #1 box in the EDIF Netlist Reader Settings dialog box. See Compiling Projects with MAX+PLUS II Software for more information.
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The ACF incorporates the following assignments from FPGA Express software and passes them to the MAX+PLUS II software:
- The Altera device family and optional specific device and speed grade specified in the Create Implementation dialog box
- The global project logic synthesis style specified in the Create Implementation dialog box
- The Clock frequency (fMAX) specified in the Create Implementation dialog box or the Clocks constraint table
- Clock speeds (tPD) specified in the Clocks constraint table
- Path group constraints specified in the Paths constraint table
- Pin assignments; settings for the Slow Slew Rate and Fast I/O logic options; and input-to-setup (tSU) and clock-to-output (tCO) delays specified in the Ports constraint table
Figure 1 shows an example of a typical ACF generated by the FPGA Express software.
Figure 1. FPGA Express-Generated Assignment & Configuration File
CHIP my_chip
DEVICE = EPF10K100GC503-3 {synopsys};
"|_CONFIG" : PIN = P40 {synopsys};
"|_STATUS" : PIN = P41 {synopsys};
GLOBAL_PROJECT_SYNTHESIS_ASSIGNMENT_OPTIONS
DEVICE_FAMILY = FLEX10K {synopsys};
STYLE = WYSIWYG {synopsys};
OPTIMIZE_FOR_SPEED = 5 {synopsys};
AUTO_GLOBAL_CLOCK = ON {synopsys};
LOGIC_OPTIONS
"|TX_FIFOA_D6" : IO_CELL_REGISTER = ON {synopsys};
"|DEST_RAM_D6" : SLOW_SLEW_RATE = ON {synopsys};
"|DEST_RAM_D5" : SLOW_SLEW_RATE = OFF {synopsys};
COMPILER_INTERFACES_CONFIGURATION
EDIF_INPUT_VCC = VDD {synopsys};
EDIF_INPUT_GND = GND {synopsys};
EDIF_INPUT_USE_LMF1 = ON {synopsys};
EDIF_INPUT_LMF1 = "my_chip.lmf" {synopsys};
TIMING_POINT
FREQUENCY = 50MHz {synopsys};
"CLK80" : FREQUENCY = 80MHz {synopsys};
"G" : FREQUENCY = 25MHz {synopsys};
TPD = 10ns {synopsys};
"inp1" : TSU = 20ns {synopsys};
"out1" : TCO = 15ns {synopsys};
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FPGA Express-generated ACFs show the Fast I/O logic option as IO_CELL_REGISTER. The MAX+PLUS II software automatically interprets this assignment as a FAST_IO assignment. |
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Altera does not warrant that this solution will work for the customer's intended purpose and disclaims all liability for use of or reliance on the solution.
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