Instantiating LPM Functions in Verilog HDL
You can enter library of parameterized modules (LPM) functions in your Verilog HDL design. The MAX+PLUS® II software supports all LPM functions except the truth table, finite state machine, and pad functions. The FPGA Express software supports all LPM functions that are supported in the MAX+PLUS II software except the lpm_and, lpm_or, lpm_xor, and lpm_mux functions. Choose Megafunctions/LPM from the MAX+PLUS II Help menu for detailed information on all LPM functions.
To instantiate an LPM function in a Verilog HDL design, follow these steps:
- Use a Module Instantiation to instantiate an LPM function. You must associate all parameters, and only positional association is allowed.
Figure 1 shows an example of instantiating an lpm_ram_dq function in Verilog HDL.
Figure 1. Verilog HDL Design File with lpm_ram_dq Instantiation
// RAM design
module design(din, we, clk, addr, dat);
input [15:0] din;
input we, clk;
input [3:0] addr;
output [15:0] dat;
supply1 vcc;
lpm_ram_dq #(
16, // LPM_WIDTH
"LPM_RAM_DQ", // LPM_TYPE
4, // LPM_WIDTHAD
16, // LPM_NUMWORDS
"UNUSED", // LPM_FILE
"UNREGISTERED", // LPM_INDATA
"UNREGISTERED", // LPM_ADDRESS_CONTROL
"UNREGISTERED" // LPM_OUTDATA
)
u1(
.data(din),
.address(addr),
.we(we),
.q(dat),
.inclock(vcc),
.outclock(clk)
);
endmodule
- Continue with the steps necessary to complete your Verilog HDL design file, as described in Creating Verilog HDL Designs for Use with
MAX+PLUS II Software.
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