Analyzing Estimated Timing with the FPGA Express Time Tracker
You can use the FPGA Express Time Tracker static timing analyzer to display estimated delays of critical paths in your project. This timing analyzer provides timing information and a detailed listing of critical paths.
To use the Time Tracker timing analyzer, follow these steps:
- Select the design implementation icon in the Chips window, press Button 2, and choose the View Results commmand from the pop-up menu to display the Time Tracker tabs.
- Analyze the timing of your design by viewing the different tables within the Clocks, Paths, and Ports Time Tracker tabs:
- To analyze the Clock frequency (fMAX), select the Clocks tab. The table on the Clocks tab contains a column showing the actual Clock frequency for each Clock in your design next to the desired frequency derived from your timing constraints. Clocks that fail to meet their constraints are highlighted in red.
- To check critical timing paths, select the Paths tab. The table on the Paths tab contains an Est. Delay column displaying path delays. Paths that fail to meet constraints are highlighted in red. You can select a path or path group to display additional tables with increasing detail, in order to identify exactly which paths failed to meet their timing constraints.
- To view I/O port delays, select the Ports tab. The Ports tab displays the slack for each I/O port, i.e., the Clock period minus the propagation delay through the port in the Input Slack column for input ports and the Output Slack column for output ports. Negative values are highlighted in red, indicating that the propagation delay exceeds the Clock period, causing a timing violation.
- If necessary, change the design logic or adjust your timing constraints as described in Assigning Pins, Logic Options, and tSU, tCO & tPD Timing Constraints, then re-optimize the design.
- Continue with the steps necessary to process your design, as described in Synthesizing & Optimizing VHDL or Verilog HDL Files with FPGA Express Software.
Analyzing Estimated Timing with the FPGA Express Time Tracker
You can use the FPGA Express Time Tracker static timing analyzer to display estimated delays of critical paths in your project. This timing analyzer provides timing information and a detailed listing of critical paths.
To use the Time Tracker timing analyzer, follow these steps:
- Select the design implementation icon in the Chips window, press Button 2, and choose the View Results commmand from the pop-up menu to display the Time Tracker tabs.
- Analyze the timing of your design by viewing the different tables within the Clocks, Paths, and Ports Time Tracker tabs:
- To analyze the Clock frequency (fMAX), select the Clocks tab. The table on the Clocks tab contains a column showing the actual Clock frequency for each Clock in your design next to the desired frequency derived from your timing constraints. Clocks that fail to meet their constraints are highlighted in red.
- To check critical timing paths, select the Paths tab. The table on the Paths tab contains an Est. Delay column displaying path delays. Paths that fail to meet constraints are highlighted in red. You can select a path or path group to display additional tables with increasing detail, in order to identify exactly which paths failed to meet their timing constraints.
- To view I/O port delays, select the Ports tab. The Ports tab displays the slack for each I/O port, i.e., the Clock period minus the propagation delay through the port in the Input Slack column for input ports and the Output Slack column for output ports. Negative values are highlighted in red, indicating that the propagation delay exceeds the Clock period, causing a timing violation.
- If necessary, change the design logic or adjust your timing constraints as described in Assigning Pins, Logic Options, and tSU, tCO & tPD Timing Constraints, then re-optimize the design.
- Continue with the steps necessary to process your design, as described in Synthesizing & Optimizing VHDL or Verilog HDL Files with FPGA Express Software.
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