| Table 1. MAX+PLUS II Directory Organization
|
| Directory
| Description
|
| ./synopsys/bin | Contains script programs to convert Synopsys timing constraints into MAX+PLUS II Assignment & Configuration File (.acf) format, and to analyze VHDL System Simulator simulation models.
|
| ./synopsys/config
| Contains sample .synopsys_dc.setup and .synopsys_vss.setup files.
|
| ./synopsys/examples
| Contains sample files, including those discussed in these ACCESS Key Guidelines.
|
| ./synopsys/library/alt_pre/<device family>/src
| Contains VHDL simulation libraries for functional simulation of VHDL projects.
|
| ./synopsys/library/alt_pre/verilog/src
| Contains the Verilog HDL functional simulation
library for Verilog HDL projects.
|
| ./synopsys/library/alt_pre/vital/src
| Contains the VITAL 95 simulation library. You use this library when you perform functional simulation of the design before compiling it with the MAX+PLUS II software.
|
| ./synopsys/library/alt_syn//<device family>/lib
| Contains interface files for the MAX+PLUS II/Synopsys interface. Technology libraries in this directory allow the Design Compiler and FPGA Compiler to map designs to Altera® device architectures.
|
| ./synopsys/library/alt_mf/src
| Contains behavioral VHDL models of some Altera macrofunctions, along with their component declarations. The a_81mux, a_8count, a_8fadd, and a_8mcomp macrofunctions are currently supported. Libraries in this directory allow you to instantiate, synthesize, and simulate these macrofunctions.
|
| ./synopsys/library/alt_post/syn/lib
| Contains the post-synthesis library for technology mapping.
|
| ./synopsys/library/alt_post/sim/src
| Contains the VHDL source files for the VITAL 95-compliant library. You use this library when you perform simulation of the design after compiling it with the MAX+PLUS II software.
|
Literature
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