Using Synopsys PrimeTime & MAX+PLUS II Software

The following topics describe how to use the Synopsys PrimeTime and MAX+PLUS^® II software. Click on one of the following topics for information:

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Setting Up the MAX+PLUS II/Synopsys Working Environment

• Software Requirements
• MAX+PLUS II/Synopsys Interface File Organization
• MAX+PLUS II Project File Structure

Timing Verification

• Timing Verification Flow
• Preparing Files for Timing Verification with PrimeTime Software using the genpt Utility

Related Topics:

• Go to the following topics in these MAX+PLUS II ACCESS^SM Key topics for related information:
  • Compiling Projects with MAX+PLUS II Software
  • Programming Altera Devices
  • Using Synopsys Design Compiler or FPGA Compiler & MAX+PLUS II Software
  • Using Synopsys FPGA Express and MAX+PLUS II Software
  • Using Synopsys VSS & MAX+PLUS II Software
• Go to the following topics, which are available on the web, for additional information:
  • MAX+PLUS II Development Software
  • Altera Programming Hardware
  • Synopsys web site (http://www.synopsys.com)

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Setting Up the MAX+PLUS II/Synopsys Working Environment

To use the MAX+PLUS^® II software with Synopsys software, you must first install the MAX+PLUS II software, then establish an environment that facilitates entering and processing designs by modifying your Synopsys configuration files. The MAX+PLUS II/Synopsys interface is installed automatically when you install the MAX+PLUS II software on your workstation. Go to MAX+PLUS II Installation in the MAX+PLUS II Getting Started manual for more information on installation and details on the directories that are created during MAX+PLUS II installation. Go to MAX+PLUS II/Synopsys Interface File Organization for information about the MAX+PLUS II/Synopsys directories that are created during MAX+PLUS II installation.

The information presented here assumes that you are using C shell and that your MAX+PLUS II system directory is /usr/maxplus2. If not, you must use the appropriate syntax and procedures to set environment variables for your shell.

To set up your working environment for the MAX+PLUS II/Synopsys interface, follow these steps:

1. Ensure that you have correctly installed the MAX+PLUS II and Synopsys software versions described in the MAX+PLUS II/Synopsys Software Requirements.

2. Add technology, synthetic, and link library settings to your .synopsys_dc.setup configuration file, as described in Setting Up Design Compiler & FPGA Compiler Configuration Files.

   To use the DesignWare interface with FLEX® 6000, FLEX 8000, and FLEX 10K devices, follow the steps in Setting Up the DesignWare Interface.

3. Add simulation library settings to your .synopsys_vss.setup file, and analyze the libraries, as described in Setting Up VSS Configuration Files.

4. Add the /usr/maxplus2/bin directory to the PATH environment variable in your .cshrc file in order to run the MAX+PLUS II software.
   (Optional) Change the path in the first line of the perl script files, which are located in the $ALT_HOME/synopsys/bin directory to specify the correct path of your local perl executable file.

Related Topics:

• Go to the following topics, which are available on the web, for additional information:
  • FLEX Devices
  • MAX+PLUS II Getting Started version 8.1 (5.4 MB)
  • This manual is also available in 4 parts:
    • Preface & Section 1: MAX+PLUS II Installation
    • Section 2: MAX+PLUS II - A Perspective
    • Section 3: MAX+PLUS II Tutorial
    • Appendices, Glossary & Index

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MAX+PLUS II/Synopsys Interface File Organization

Table 1 shows the MAX+PLUS^® II/Synopsys interface subdirectories that are created in the MAX+PLUS II system directory (by default, the /usr/maxplus2 directory) during the MAX+PLUS II software installation. For information on the other directories that are created during the MAX+PLUS II software installation, see "MAX+PLUS II File Organization" in MAX+PLUS II Installation in the MAX+PLUS II Getting Started manual.

You must add the /usr/maxplus2/bin directory to the PATH environment variable in your .cshrc file in order to run the MAX+PLUS II software.

Table 1. MAX+PLUS II Directory Organization
Directory	Description
./synopsys/bin	Contains script programs to convert Synopsys timing constraints into MAX+PLUS II Assignment & Configuration File (.acf) format, and to analyze VHDL System Simulator simulation models.
./synopsys/config	Contains sample .synopsys_dc.setup and .synopsys_vss.setup files.
./synopsys/examples	Contains sample files, including those discussed in these ACCESS Key Guidelines.
./synopsys/library/alt_pre/<device family>/src	Contains VHDL simulation libraries for functional simulation of VHDL projects.
./synopsys/library/alt_pre/verilog/src	Contains the Verilog HDL functional simulation library for Verilog HDL projects.
./synopsys/library/alt_pre/vital/src	Contains the VITAL 95 simulation library. You use this library when you perform functional simulation of the design before compiling it with the MAX+PLUS II software.
./synopsys/library/alt_syn//<device family>/lib	Contains interface files for the MAX+PLUS II/Synopsys interface. Technology libraries in this directory allow the Design Compiler and FPGA Compiler to map designs to Altera® device architectures.
./synopsys/library/alt_mf/src	Contains behavioral VHDL models of some Altera macrofunctions, along with their component declarations. The a_81mux, a_8count, a_8fadd, and a_8mcomp macrofunctions are currently supported. Libraries in this directory allow you to instantiate, synthesize, and simulate these macrofunctions.
./synopsys/library/alt_post/syn/lib	Contains the post-synthesis library for technology mapping.
./synopsys/library/alt_post/sim/src	Contains the VHDL source files for the VITAL 95-compliant library. You use this library when you perform simulation of the design after compiling it with the MAX+PLUS II software.

Related Topics:

• Go to the following topics, which are available on the web, for additional information:
  • MAX+PLUS II Getting Started version 8.1 (5.4 MB)
  • This manual is also available in 4 parts:
    • Preface & Section 1: MAX+PLUS II Installation
    • Section 2: MAX+PLUS II - A Perspective
    • Section 3: MAX+PLUS II Tutorial
    • Appendices, Glossary & Index

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MAX+PLUS II Project File Structure

In MAX+PLUS^® II, a project name is the name of a top-level design file, without the filename extension. This design file can be an EDIF, Verilog HDL, or VHDL netlist file; an AHDL^™ TDF; or any other MAX+PLUS II-supported design file. The EDIF netlist file must be created by Synopsys and imported into MAX+PLUS II as an EDIF Input File.

MAX+PLUS II stores the connectivity data on the links between design files in a hierarchical project in a Hierarchy Interconnect File (.hif), but refers to the entire project only by its project name. The MAX+PLUS II Compiler uses the HIF to build a single, fully flattened project database that integrates all the design files in a project hierarchy.

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MAX+PLUS II/Synopsys PrimeTime Timing Verification Flow

Figure 1 shows the project timing verification flow for the MAX+PLUS^® II/Synopsys PrimeTime interface.

Figure 1. MAX+PLUS II/Synopsys PrimeTime Project Timing Verification Flow

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Preparing Files for Timing Verification with PrimeTime Software Using the genpt Utility

After you have compiled a project and generated an EDIF Output File (.edo), Verilog Output File (.vo), or VHDL Output File (.vho) with the MAX+PLUS^® II software, you can use Synopsys PrimeTime software to perform timing verification. The Altera-provided genpt utility converts EDIF, Verilog HDL, and VHDL output files for use with Synopsys PrimeTime software.

To prepare MAX+PLUS II-generated EDIF, Verilog HDL, or VHDL output files for timing verification with the Synopsys PrimeTime software, follow these steps:

1. Set up your working environment correctly, as described in Setting Up the MAX+PLUS II/Synopsys Working Environment. Make sure that you have specified the correct path of your local Perl executable, as described in step 4 of that procedure, and that the path in the genpt utility points to that executable.

2. Generate an EDIF Output File (.edo), Verilog Output File (.vo), or VHDL Output File (.vho) and a Standard Delay Format (SDF) Output File (.sdo) by compiling your design with the MAX+PLUS II software, as described in Compiling Projects with MAX+PLUS II Software.

3. Use the genpt utility to convert the EDIF, Verilog HDL, or VHDL output file(s) to PrimeTime-compatible files by typing the following command at the UNIX prompt:

   genpt (-verilog | -vhdl | -edif) <design name> [<output netlist filename>] 

   where <design name> is the name of the MAX+PLUS II-generated output file, without the extension. For example, you can type genpt -vhdl fifo  at the UNIX prompt to convert MAX+PLUS II-generated fifo.vhd and fifo.sdo files into PrimeTime-compatible VHDL and SDF files.

   Based on your settings, the genpt utility generates the following files:

   • A PrimeTime-compatible Verilog HDL file <design name>_pt.v
   • A VHDL file <design name>_pt.vhd or an EDIF netlist file <design name>_pt.edif
   • An SDF file <design name>_pt.sdf.

   If the project contains RAM, ROM, dual-port RAM, or clklock functions, the genpt utility generates a <design name>_<type>.db file, where <type> is ram, rom, dpram, or cklk, which contains compiled STAMP library cell models for the PrimeTime software. The genpt utility also generates a <design name>_setup.pt PrimeTime setup file, which contains PrimeTime setup commands for compiling generated STAMP models and for reading in the EDIF, Verilog, or VHDL file and the SDF file.

4. Start the PrimeTime software by typing primetime  at the UNIX prompt. You can also type pt_shell  at the UNIX prompt to run the PrimeTime software in command-line mode.

5. Source the <design name>_setup.pt PrimeTime setup file. Refer to Synopsys PrimeTime documentation for information on how to perform timing verification with the PrimeTime software.