Performing a Timing Simulation with VSS Software

Once the MAX+PLUS^® II software has compiled a project and generated a VHDL Output File (.vho) and an optional Standard Delay Format (SDF) Output File (.sdo), you can perform timing simulation with the Synopsys VHDL Simulator Software (VSS).

To simulate a VHDL Output File with VSS, follow these steps:

Be sure to set up the working environment correctly, as described in the following topics:

• Setting Up the MAX+PLUS II/Synopsys Working Environment
• Setting Up Design Compiler & FPGA Compiler Configuration Files
• Setting Up the DesignWare Interface
• Setting Up VSS Configuration Files

1. Generate a VHDL Output File (.vho) and an optional SDF Output File (.sdo), as described in Compiling Projects with MAX+PLUS II Software.

2. (Optional) Analyze the VITAL 95-compliant alt_vtl library , then back-annotate timing information through the SDF Output File:

   1. Use the analyze_vss script to analyze the alt_vtl Post-Routing Timing Simulation library, as described in Setting Up VSS Configuration Files.

   2. Enter the following command to back-annotate timing information through the SDF Output File:

      vhdlsim -sdf_top /<design name>/<design name> -sdf
<design name>.sdo

3. Simulate the VHDL Output File with the VSS software.

Related Topics:

• Go to the VSS User's Guide for more details on post-routing simulation.

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