Altera Simulation Libraries

Altera provides simulation libraries for both pre-routing functional simulation and post-routing timing simulation.

Pre-Routing Functional Simulation Libraries (VITAL-Compliant)

The /usr/maxplus2/synopsys/library/alt_pre/vital/src directory contains Altera^®-provided VHDL simulation models in VITAL 95 format. This library contains functional descriptions of all primitives that appear in Altera-specific technology libraries. These libraries allow you to perform a functional or pre-routing simulation that verifies the netlist structure generated by the Synopsys Design Compiler or FPGA Compiler software. Altera provides the flex.cmp and flex.vhd files in the /usr/maxplus2/synopsys/library/alt_pre/vital/src directory.

Similarly, the /usr/maxplus2/synopsys/library/alt_pre/verilog/src directory contains Altera-provided Verilog HDL simulation models for all device families. The altera.v file can be used for simulation with the Cadence Verilog-XL simulator.

Pre-Routing Functional Simulation Libraries with Estimated Timing Information

The /usr/maxplus2/synopsys/library/alt_pre/<device family>/src directory contains Altera^®-provided VHDL simulation libraries, which give both functional and area descriptions of all primitives that appear in all Altera technology libraries. These simulation libraries allow you to verify the function of VHDL projects, with estimated timing, after synthesizing them with the Synopsys Design Compiler or FPGA Compiler, but before submitting them to MAX+PLUS^® II software for compilation.

Altera provides an encrypted Full Timing Structural Model (FTSM) and a Full Timing Gate-Level Simulation model (FTGS) for the VHDL simulation libraries listed in Table 1.

Table 1. VHDL Functional Simulation Libraries
Device Family	Functional Simulation Libraries	Device Family	Functional Simulation Libraries
FLEX® 10K	flex10k_FTSM.vhd.E flex10k_fpga_FTSM.vhd.E flex10k_FTGS.vhd.E flex10k_fpga_FTGS.vhd.E flex10k_components.vhd flex10k_fpga_components.vhd	MAX® 9000	max9000_FTSM.vhd.E max9000_fpga_FTSM.vhd.E max9000_FTGS.vhd.E max9000_fpga_FTGS.vhd.E max9000_components.vhd max9000_fpga_components.vhd
FLEX 8000	flex8000_FTSM.vhd.E flex8000_fpga_FTSM.vhd.E flex8000_FTGS.vhd.E flex8000_fpga_FTGS.vhd.E flex8000_components.vhd flex8000_fpga_components.vhd	MAX 7000	max7000_FTSM.vhd.E max7000_fpga_FTSM.vhd.E max7000_FTGS.vhd.E max7000_fpga_FTGS.vhd.E max7000_components.vhd max7000_fpga_components.vhd
FLEX 6000	flex6000_FTSM.vhd.E flex6000_fpga_FTSM.vhd.E flex6000_FTGS.vhd.E flex6000_fpga_FTGS.vhd.E flex6000_components.vhd flex6000_fpga_components.vhd	MAX 5000 & Classic®	max5000_FTSM.vhd.E max5000_fpga_FTSM.vhd.E max5000_FTGS.vhd.E max5000_fpga_FTGS.vhd.E max5000_components.vhd max5000_fpga_components.vhd

Post-Routing Timing Simulation Libraries

The /usr/maxplus2/synopsys/library/alt_post/sim/src directory contains the Altera^®-provided library files for performing timing simulation of designs that have been compiled with the MAX+PLUS II software. The VITAL 95-compliant post-simulation source files included in this directory are alt_vtl.vhd and alt_vtl.cmp. See Performing a Timing Simulation with VSS Software for more information.

Related Links:

• Go to the following topics for additional information:
  • FLEX Devices
  • MAX Devices
  • Classic Device Family

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