Using Synopsys VSS & MAX+PLUS II Software

The following topics describe how to use the Synopsys VHDL System Simulator (VSS) and MAX+PLUS^® II software. Choose one of the following topics for information:

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Setting Up the MAX+PLUS II/Synopsys Working Environment

Software Requirements
Setting Up VSS Configuration Files
Simulation Libraries
MAX+PLUS II/Synopsys Interface File Organization
MAX+PLUS II Project File Structure

Functional Simulation

Design Entry Flow
Performing a Pre-Routing or Functional Simulation with VSS Software

Timing Simulation

Project Simulation Flow
Performing a Timing Simulation with VSS Software

Setting Up the MAX+PLUS II/Synopsys Working Environment

To use the MAX+PLUS^® II software with Synopsys software, you must first install the MAX+PLUS II software, then establish an environment that facilitates entering and processing designs by modifying your Synopsys configuration files. The MAX+PLUS II/Synopsys interface is installed automatically when you install the MAX+PLUS II software on your workstation. Go to MAX+PLUS II Installation in the MAX+PLUS II Getting Started manual for more information on installation and details on the directories that are created during MAX+PLUS II installation. Go to MAX+PLUS II/Synopsys Interface File Organization for information about the MAX+PLUS II/Synopsys directories that are created during MAX+PLUS II installation.

The information presented here assumes that you are using C shell and that your MAX+PLUS II system directory is /usr/maxplus2. If not, you must use the appropriate syntax and procedures to set environment variables for your shell.

To set up your working environment for the MAX+PLUS II/Synopsys interface, follow these steps:

Ensure that you have correctly installed the MAX+PLUS II and Synopsys software versions described in the MAX+PLUS II/Synopsys Software Requirements.
Add technology, synthetic, and link library settings to your .synopsys_dc.setup configuration file, as described in Setting Up Design Compiler & FPGA Compiler Configuration Files.

To use the DesignWare interface with FLEX^® 6000, FLEX 8000, and FLEX 10K devices, follow the steps in Setting Up the DesignWare Interface.
Add simulation library settings to your .synopsys_vss.setup file, and analyze the libraries, as described in Setting Up VSS Configuration Files.
Add the /usr/maxplus2/bin directory to the PATH environment variable in your .cshrc file in order to run the MAX+PLUS II software.
(Optional) Change the path in the first line of the perl script files, which are located in the $ALT_HOME/synopsys/bin directory to specify the correct path of your local perl executable file.

MAX+PLUS II/Synopsys Software Requirements

The following applications are used to generate, process, synthesize, and verify a project with MAX+PLUS^® II and Synopsys software:

Synopsys

Altera

version 1998.02:
Design Compiler
FPGA Compiler
Design Analyzer (optional)
VHDL Compiler

HDL Compiler for Verilog
VHDL System Simulator (VSS) (optional)
PrimeTime version 1998.02-PT2.1(optional)

MAX+PLUS II version 9.3

Compilation with the Synopsys Design Compiler and FPGA Compiler is available only on Sun SPARCstations running Solaris 2.4 or higher.

The MAX+PLUS II read.me file provides up-to-date information on which versions of Synopsys applications are supported by the current version of MAX+PLUS II. It also provides information on installation and operating requirements. You should read the read.me file on the CD-ROM before installing the MAX+PLUS II software. After installation, you can open the read.me file from the MAX+PLUS II Help menu.

Setting Up VSS Configuration Files

The .synopsys_vss.setup file contains the mapping information that directs the VHDL System Simulator (VSS) Software to use Altera^®-supplied Altera Simulation Libraries during simulation. To configure your environment for the MAX+PLUS^® II/Synopsys interface, follow these steps:

Add the lines shown in Figure 1 to your .synopsys_vss.setup file. Altera provides a sample setup file, .synopsys_vss.setup, in the /usr/maxplus2/synopsys/config directory. See Figure 1.

Figure 1. Sample .synopsys_vss.setup File

WORK > DEFAULT
DEFAULT            : .

altera             : /usr/maxplus2/synopsys/library/alt_mf/lib

flex_vtl           : /usr/maxplus2/synopsys/library/alt_pre/vital/
                        lib/flex_vtl
alt_vtl            : /usr/maxplus2/synopsys/library/alt_post/sim/
                        lib/alt_vtl
flex10k_ftsm       : /usr/maxplus2/synopsys/library/alt_pre/flex10k/
                        lib/flex10k_ftsm
flex10k_ftgs       : /usr/maxplus2/synopsys/library/alt_pre/flex10k/
                        lib/flex10k_ftgs
max9000_ftsm       : /usr/maxplus2/synopsys/library/alt_pre/max9000/
                        lib/max9000_ftsm
max9000_ftgs       : /usr/maxplus2/synopsys/library/alt_pre/max9000/
                        lib/max9000_ftgs
flex8000_ftsm      : /usr/maxplus2/synopsys/library/alt_pre/flex8000/
                       lib/flex8000_ftsm
flex8000_ftgs      : /usr/maxplus2/synopsys/library/alt_pre/flex8000/
                       lib/flex8000_ftgs
max7000_ftsm       : /usr/maxplus2/synopsys/library/alt_pre/max7000/
                        lib/max7000_ftsm
max7000_ftgs       : /usr/maxplus2/synopsys/library/alt_pre/max7000/
                        lib/max7000_ftgs
flex6000_ftsm      : /usr/maxplus2/synopsys/library/alt_pre/flex6000/
                       lib/flex6000_ftsm
flex6000_ftgs      : /usr/maxplus2/synopsys/library/alt_pre/flex6000/
                       lib/flex6000_ftgs
max5000_ftsm       : /usr/maxplus2/synopsys/library/alt_pre/max5000/
                        lib/max5000_ftsm
max5000_ftgs       : /usr/maxplus2/synopsys/library/alt_pre/max5000/
                        lib/max5000_ftgs
flex10k_fpga_ftsm  : /usr/maxplus2/synopsys/library/alt_pre/flex10k/
                        lib/flex10k_fpga_ftsm
flex10k_fpga_ftsm  : /usr/maxplus2/synopsys/library/alt_pre/flex10k/
                        lib/flex10k_fpga_ftgs
max9000_fpga_ftsm  : /usr/maxplus2/synopsys/library/alt_pre/max9000/
                        lib/max9000_fpga_ftsm
max9000_fpga_ftgs  : /usr/maxplus2/synopsys/library/alt_pre/max9000/
                        lib/max9000_fpga_ftgs
flex8000_fpga_ftsm : /usr/maxplus2/synopsys/library/alt_pre/flex8000/
                        lib/flex8000_fpga_ftsm
flex8000_fpga_ftgs : /usr/maxplus2/synopsys/library/alt_pre/flex8000/
                        lib/flex8000_fpga_ftgs
max7000_fpga_ftsm  : /usr/maxplus2/synopsys/library/alt_pre/max7000/
                        lib/max7000_fpga_ftsm
max7000_fpga_ftgs  : /usr/maxplus2/synopsys/library/alt_pre/max7000/
                        lib/max7000_fpga_ftgs
flex6000_fpga_ftsm : /usr/maxplus2/synopsys/library/alt_pre/flex6000/
                        lib/flex6000_fpga_ftsm
flex6000_fpga_ftgs : /usr/maxplus2/synopsys/library/alt_pre/flex6000/
                        lib/flex6000_fpga_ftgs
max5000_fpga_ftsm  : /usr/maxplus2/synopsys/library/alt_pre/max5000/
                        lib/max5000_fpga_ftsm
max5000_fpga_ftgs  : /usr/maxplus2/synopsys/library/alt_pre/max5000/
                        lib/max5000_fpga_ftgs

The variables in the .synopsys_vss setup file perform the following functions:

The WORK variable specifies your working directory, i.e., the directory where you start the Synopsys tools. If not explicitly specified elsewhere, the results of any analysis or compilation are written to this directory. The first line of the file shown in Figure 1 maps WORK to the design library variable called DEFAULT.
The DEFAULT variable is used to create library aliases, which allows you to map the WORK variable to various paths. In Figure 1, the DEFAULT variable specifies the current directory.
The altera library is listed to allow you to simulate the architecture control logic functions in the alt_mf library.
The remaining lines in the file specify the path and name of the directories that contain the device simulation libraries for Altera device families.

Analyze the target device simulation library to ensure that the correct timing and functional information is provided to VSS. Analyzing the simulation library produces VSS simulation models of the primitives that appear in all Altera-provided technology libraries.

You can analyze device simulation libraries by using the Altera-provided shell script analyze_vss:

Add the /usr/maxplus2/synopsys/bin directory, which contains the analyze_vss scripts, to the PATH environment variable in your .cshrc file.
Make sure that you have write privileges for the /usr/maxplus2/synopsys/library/alt_pre/<device family> directory because the analyzed model is placed in the /usr/maxplus2/synopsys/library/alt_pre/<device family>/lib directory and the analysis log file is placed in the ./synopsys/library/alt_pre/<device family>/src directory.

Run the analyze_vss shell script by typing analyze_vss

at the dc_shell prompt. When you run the analyze_vss shell script, you are prompted to select the appropriate device family simulation model(s) for analysis. Figure 2 shows the analyze_vss shell script.

Figure 2. The analyze_vss Shell Script

Type the full pathname of the directory where the MAX+PLUS^® II software is installed (default: /usr/maxplus2):

<MAX+PLUS II system directory>

Analyze VSS Simulation Models:
1. flex10k_FTGS
2. flex10k_FTSM
3. flex10k_fpga_FTGS
4. flex10k_fpga_FTSM
5. max9000_FTGS
6. max9000_FTSM
7. max9000_fpga_FTGS
8. max9000_fpga_FTSM
9. flex8000_FTGS
10. flex8000_FTSM
11. flex8000_fpga_FTGS
12. flex8000_fpga_FTSM
13. max7000_FTGS
14. max7000_FTSM
15. max7000_fpga_FTGS
16. max7000_fpga_FTSM
17. flex6000_FTGS
18. flex6000_FTSM
19. flex6000_fpga_FTGS
20. flex6000_fpga_FTSM
21. max5000_FTGS
22. max5000_FTSM
23. max5000_fpga_FTGS
24. max5000_fpga_FTSM
25. alt_vtl
26. flex_vtl
27. Quit

Enter one or more numbers: <device library numbers>

Check the log file to make sure that no errors occurred during the analysis of the simulation models.

Use VSS to simulate your pre-routed VHDL design.

Altera Simulation Libraries

Altera provides simulation libraries for both pre-routing functional simulation and post-routing timing simulation.

Pre-Routing Functional Simulation Libraries (VITAL-Compliant)

The /usr/maxplus2/synopsys/library/alt_pre/vital/src directory contains Altera^®-provided VHDL simulation models in VITAL 95 format. This library contains functional descriptions of all primitives that appear in Altera-specific technology libraries. These libraries allow you to perform a functional or pre-routing simulation that verifies the netlist structure generated by the Synopsys Design Compiler or FPGA Compiler software. Altera provides the flex.cmp and flex.vhd files in the /usr/maxplus2/synopsys/library/alt_pre/vital/src directory.

Similarly, the /usr/maxplus2/synopsys/library/alt_pre/verilog/src directory contains Altera-provided Verilog HDL simulation models for all device families. The altera.v file can be used for simulation with the Cadence Verilog-XL simulator.

Pre-Routing Functional Simulation Libraries with Estimated Timing Information

The /usr/maxplus2/synopsys/library/alt_pre/<device family>/src directory contains Altera^®-provided VHDL simulation libraries, which give both functional and area descriptions of all primitives that appear in all Altera technology libraries. These simulation libraries allow you to verify the function of VHDL projects, with estimated timing, after synthesizing them with the Synopsys Design Compiler or FPGA Compiler, but before submitting them to MAX+PLUS^® II software for compilation.

Altera provides an encrypted Full Timing Structural Model (FTSM) and a Full Timing Gate-Level Simulation model (FTGS) for the VHDL simulation libraries listed in Table 1.

Table 1. VHDL Functional Simulation Libraries
Device Family	Functional Simulation Libraries	Device Family	Functional Simulation Libraries
FLEX^® 10K	flex10k_FTSM.vhd.E flex10k_fpga_FTSM.vhd.E flex10k_FTGS.vhd.E flex10k_fpga_FTGS.vhd.E flex10k_components.vhd flex10k_fpga_components.vhd	MAX^® 9000	max9000_FTSM.vhd.E max9000_fpga_FTSM.vhd.E max9000_FTGS.vhd.E max9000_fpga_FTGS.vhd.E max9000_components.vhd max9000_fpga_components.vhd
FLEX 8000	flex8000_FTSM.vhd.E flex8000_fpga_FTSM.vhd.E flex8000_FTGS.vhd.E flex8000_fpga_FTGS.vhd.E flex8000_components.vhd flex8000_fpga_components.vhd	MAX 7000	max7000_FTSM.vhd.E max7000_fpga_FTSM.vhd.E max7000_FTGS.vhd.E max7000_fpga_FTGS.vhd.E max7000_components.vhd max7000_fpga_components.vhd
FLEX 6000	flex6000_FTSM.vhd.E flex6000_fpga_FTSM.vhd.E flex6000_FTGS.vhd.E flex6000_fpga_FTGS.vhd.E flex6000_components.vhd flex6000_fpga_components.vhd	MAX 5000 & Classic^®	max5000_FTSM.vhd.E max5000_fpga_FTSM.vhd.E max5000_FTGS.vhd.E max5000_fpga_FTGS.vhd.E max5000_components.vhd max5000_fpga_components.vhd

Post-Routing Timing Simulation Libraries

The /usr/maxplus2/synopsys/library/alt_post/sim/src directory contains the Altera^®-provided library files for performing timing simulation of designs that have been compiled with the MAX+PLUS II software. The VITAL 95-compliant post-simulation source files included in this directory are alt_vtl.vhd and alt_vtl.cmp. See Performing a Timing Simulation with VSS Software for more information.

MAX+PLUS II/Synopsys Interface File Organization

Table 1 shows the MAX+PLUS^® II/Synopsys interface subdirectories that are created in the MAX+PLUS II system directory (by default, the /usr/maxplus2 directory) during the MAX+PLUS II software installation. For information on the other directories that are created during the MAX+PLUS II software installation, see "MAX+PLUS II File Organization" in MAX+PLUS II Installation in the MAX+PLUS II Getting Started manual.

You must add the /usr/maxplus2/bin directory to the PATH environment variable in your .cshrc file in order to run the MAX+PLUS II software.

Table 1. MAX+PLUS II Directory Organization
Directory	Description
./synopsys/bin	Contains script programs to convert Synopsys timing constraints into MAX+PLUS II Assignment & Configuration File (.acf) format, and to analyze VHDL System Simulator simulation models.
./synopsys/config	Contains sample .synopsys_dc.setup and .synopsys_vss.setup files.
./synopsys/examples	Contains sample files, including those discussed in these ACCESS Key Guidelines.
./synopsys/library/alt_pre/<device family>/src	Contains VHDL simulation libraries for functional simulation of VHDL projects.
./synopsys/library/alt_pre/verilog/src	Contains the Verilog HDL functional simulation library for Verilog HDL projects.
./synopsys/library/alt_pre/vital/src	Contains the VITAL 95 simulation library. You use this library when you perform functional simulation of the design before compiling it with the MAX+PLUS II software.
./synopsys/library/alt_syn//<device family>/lib	Contains interface files for the MAX+PLUS II/Synopsys interface. Technology libraries in this directory allow the Design Compiler and FPGA Compiler to map designs to Altera^® device architectures.
./synopsys/library/alt_mf/src	Contains behavioral VHDL models of some Altera macrofunctions, along with their component declarations. The `a_81mux`, `a_8count`, `a_8fadd`, and `a_8mcomp` macrofunctions are currently supported. Libraries in this directory allow you to instantiate, synthesize, and simulate these macrofunctions.
./synopsys/library/alt_post/syn/lib	Contains the post-synthesis library for technology mapping.
./synopsys/library/alt_post/sim/src	Contains the VHDL source files for the VITAL 95-compliant library. You use this library when you perform simulation of the design after compiling it with the MAX+PLUS II software.

MAX+PLUS II Project File Structure

In MAX+PLUS^® II, a project name is the name of a top-level design file, without the filename extension. This design file can be an EDIF, Verilog HDL, or VHDL netlist file; an AHDL^™ TDF; or any other MAX+PLUS II-supported design file. The EDIF netlist file must be created by Synopsys and imported into MAX+PLUS II as an EDIF Input File.

MAX+PLUS II stores the connectivity data on the links between design files in a hierarchical project in a Hierarchy Interconnect File (.hif), but refers to the entire project only by its project name. The MAX+PLUS II Compiler uses the HIF to build a single, fully flattened project database that integrates all the design files in a project hierarchy.

Synopsys Design Entry Flow

Figure 1 below shows the design entry flow for the MAX+PLUS^® II/Synopsys interface.

Figure 1. MAX+PLUS II/Synopsys Design Entry Flow

Altera-provided items are shown in blue.

Design Entry Flow

Performing a Pre-Routing or Functional Simulation with VSS Software

After you have synthesized and optimized a VHDL or Verilog HDL design with the Design Compiler or FPGA Compiler software, you can perform a pre-routing or functional simulation with the Synopsys VHDL System Simulator (VSS) software.

To perform a pre-routing/functional simulation, follow these steps:

Be sure to set up the working environment correctly, as described in the following topics:
- Setting Up the MAX+PLUS II/Synopsys Working Environment
- Setting Up Design Compiler & FPGA Compiler Configuration Files
- Setting Up the DesignWare Interface
- Setting Up VSS Configuration Files
Create a VHDL or Verilog HDL design file that follows the guidelines described in one of the following topics:
- Creating VHDL Designs for Use with MAX+PLUS II Software
- Creating Verilog HDL Designs for Use with MAX+PLUS II Software
Synthesize and optimize your design with the Design Compiler or FPGA Compiler, as described in Synthesizing & Optimizing VHDL & Verilog HDL Files with Design Compiler or FPGA Compiler Software.
Save your design as a VHDL Design File (.vhd).

VSS requires each architecture/entity pair in a VHDL Design File to have a configuration. The Configuration Declaration is necessary for simulation, but not for synthesis.
Use VSS and one of the Altera pre-routing functional simulation libraries to simulate the design.
When you are ready to compile your project with MAX+PLUS II software, save the design as an EDIF netlist file (.edf), then process it as described in Compiling Projects with MAX+PLUS II Software.

Project Simulation Flow

Figure 1 shows the project simulation flow for the MAX+PLUS^® II/Synopsys interface.

Figure 1. MAX+PLUS II/Synopsys Project Simulation Flow

Altera-provided items are shown in blue.

The MAX+PLUS II/Synopsys design environment fully supports design verification with the Synopsys VHDL System Simulator (VSS). For pre-route simulation, you can simulate a design that has been compiled with one of the Synopsys compilers. For post-route simulation, you can simulate the VHDL Output File (.vho) that MAX+PLUS II^® software generates during project compilation.

Performing a Timing Simulation with VSS Software

Once the MAX+PLUS^® II software has compiled a project and generated a VHDL Output File (.vho) and an optional Standard Delay Format (SDF) Output File (.sdo), you can perform timing simulation with the Synopsys VHDL Simulator Software (VSS).

To simulate a VHDL Output File with VSS, follow these steps:

Be sure to set up the working environment correctly, as described in the following topics:

Setting Up the MAX+PLUS II/Synopsys Working Environment
Setting Up Design Compiler & FPGA Compiler Configuration Files
Setting Up the DesignWare Interface
Setting Up VSS Configuration Files

Generate a VHDL Output File (.vho) and an optional SDF Output File (.sdo), as described in Compiling Projects with MAX+PLUS II Software.
(Optional) Analyze the VITAL 95-compliant alt_vtl library , then back-annotate timing information through the SDF Output File:
2. Use the analyze_vss script to analyze the alt_vtl Post-Routing Timing Simulation library, as described in Setting Up VSS Configuration Files.
3. Enter the following command to back-annotate timing information through the SDF Output File:
  
  vhdlsim -sdf_top /<design name>/<design name> -sdf<design name>.sdo
Simulate the VHDL Output File with the VSS software.

Programming Altera Devices

Once you have successfully compiled and simulated a project with the MAX+PLUS^® II software, you can program an Altera^® device and test it in the target circuit. Figure 1 shows the device programming flow for MAX+PLUS II software.

Figure 1. MAX+PLUS II Device Programming Flow

Altera-provided items are shown in blue.

You can program devices with Altera programming hardware and MAX+PLUS II Programmer software installed on a 486- or Pentium-based PC or a UNIX workstation, or with programming hardware and software available from other manufacturers. Table 1 shows the available Altera programming hardware options on PCs and UNIX workstations.

*Table 1. Altera Programming Hardware*
Programming Hardware Option	PCs	UNIX Work- stations	MAX® 3000A Devices	Classic® & MAX 5000 Devices	MAX 7000 & MAX 7000E Devices	MAX 7000A, MAX 7000AE, MAX 7000S MAX 9000 & MAX 9000A Devices	FLEX® 6000, FLEX 6000A, FLEX 8000, FLEX 10K, FLEX 10KA, FLEX 10KB, & FLEX 10KE Devices	In-System Programming/ Configuration
Logic Programmer card, PL-MPU Master Programming Unit, and device-specific adapters
BitBlaster™ Download Cable
ByteBlasterMV™ Download Cable

If you wish to transfer programming files from a UNIX workstation to a PC over a network with File Transfer Protocol (FTP) or other similar transfer programs, be sure to select binary transfer mode.

Programming hardware from other manufacturers varies, but typically consists of a device connected to one of the serial ports on the workstation. Various vendors, such as Data I/O and BP Microsystems, supply hardware and software for programming Altera devices.

Using Synopsys VSS & MAX+PLUS II Software

Setting Up the MAX+PLUS II/Synopsys Working Environment

Functional Simulation

Timing Simulation

Related Topics:

Setting Up the MAX+PLUS II/Synopsys Working Environment

Related Topics:

MAX+PLUS II/Synopsys Software Requirements

Setting Up VSS Configuration Files

Related Topics:

Altera Simulation Libraries

Pre-Routing Functional Simulation Libraries (VITAL-Compliant)

Pre-Routing Functional Simulation Libraries with Estimated Timing Information

Post-Routing Timing Simulation Libraries

Related Topics:

MAX+PLUS II/Synopsys Interface File Organization

Related Topics:

MAX+PLUS II Project File Structure

Synopsys Design Entry Flow

Performing a Pre-Routing or Functional Simulation with VSS Software

Related Topics:

Project Simulation Flow

Performing a Timing Simulation with VSS Software

Related Topics:

Programming Altera Devices

Figure 1. MAX+PLUS II Device Programming Flow

Table 1. Altera Programming Hardware

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