The following topics describe how to use the Synopsys VHDL System Simulator (VSS) and
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Setting Up the MAX+PLUS II/Synopsys Working Environment
- Software Requirements
- Setting Up VSS Configuration Files
- Simulation Libraries
- MAX+PLUS II/Synopsys Interface File Organization
- MAX+PLUS II Project File Structure
Functional Simulation
Timing Simulation
- Project Simulation Flow
- Initializing Registers in VHDL & Verilog Output Files for Power-Up before Simulation
- Performing a Timing Simulation with VSS Software
Related Links:
- Go to the following topics in these MAX+PLUS II
ACCESSSM Key topics for related information:- Compiling Projects with MAX+PLUS II Software
- Programming Altera Devices
- Resynthesizing a Design Using the alt.vtl Library & a MAX+PLUS II SDF Output File
- Using Synopsys Design Compiler or FPGA Compiler & MAX+PLUS II Software
- Using Synopsys FPGA Express & MAX+PLUS II Software
- Using Synopsys PrimeTime & MAX+PLUS II Software
- Go to the following topics, which are available on the web, for additional information:
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