If you are using the
- Choose Global Project Logic Synthesis (Assign menu) to open the Global Project Logic Synthesis dialog box.
- Select the appropriate logic synthesis style under the Global Project Synthesis Style:
If you turned on the Map Logic to LCELLs option in the Synplify Set Device Options dialog box when synthesizing a FLEX® device design with Synplify software, select WYSIWYG or Fast in the Global Project Synthesis Style box.or:
If you did not turn on the Map Logic to LCELLs option in the Synplify Set Device Options dialog box when synthesizing your design with Synplify software, or if you are using a MAX® orClassic™ device, select Normal in the Global Project Synthesis Style box. - For FLEX devices, choose Define Synthesis Style to display the Define Synthesis Style dialog box. Choose Advanced Options to display the Advanced Options dialog box and turn off the NOT Gate Push-Back option. Choose OK twice to close the dialog box.
- Choose OK to close the Global Project Logic Synthesis dialog box.
- Continue with the steps necessary to compile your project, as described in Compiling Projects with MAX+PLUS II Software.
Related Links:
Feedback
Did this information help you?
If no, please log onto mySupport to file a technical request or enhancement.
Altera does not warrant that this solution will work for the customer's intended purpose and disclaims all liability for use of or reliance on the solution.
