Assigning Pins
You can assign a single port to a specific pin to ensure that the signal is always associated with that pin, regardless of future changes to the project. You can specify pins in VHDL or Verilog HDL designs, or in a Synplify Design Constraints File (.sdc). If you add timing constraints or resource assignments in a separate Synplify Design Constraints File (.sdc), you must add the Synplify Design Constraints File (.sdc) to the project by adding it to the Source Files list in the Synplify window.
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If your design uses resource assignment attributes that you wish to pass to the
MAX+PLUS® II software, you should save your file in EDIF netlist file format. See Entering Resource Assignments for more information.
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VHDL Syntax
Use the following syntax to assign a pin in VHDL:
attribute altera_chip_pin_lc : string;
attribute altera_chip_pin_lc of <port name> : signal is "@<pin number(s)>";
Example:
attribute altera_chip_pin_lc : string;
attribute altera_chip_pin_lc of result : signal is
"@17, @166, @191, @152, @15, @148, @147, @149";
Verilog HDL Syntax
Use the following syntax to assign a pin in Verilog HDL:
<port name> /* synthesis altera_chip_pin_lc="@<pin number(s)>" */;
Example:
output [7:0] sum /* synthesis altera_chip_pin_lc="@17, @166, @191, @152, ¥
@15, @148, @147, @149" */;
Synplify Design Constraints File Syntax
Use the following syntax to assign a pin in a Synplify Design Constraints file:
define_attribute <port name> altera_chip_pin_lc "@<pin number>"
Example:
define_attribute {DATA0[7:0]} altera_chip_pin_lc "@115,@116,@117,
@118,@119,@120,@121,@122"
Related Links:
- Refer to the following sources for related information:
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Literature
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