The
VHDL & Verilog HDL Design Files
When you use Synplicity Synplify software, you can assign a limited subset of these resource assignments by specifying attributes in the Synplify Design Constraints File (.sdc) or in the VHDL or Verilog HDL design files. The Synplify software automatically incorporates these attributes into the EDIF netlist file(s) generated from the HDL design files. MAX+PLUS II then automatically converts assignment information from the EDIF Input File into the ACF format. The following topics describe how to make MAX+PLUS II-compatible resource assignments before design processing with the Synplify software:
- Assigning Pins
- Assigning the Implement in EAB Logic Option
- Modifying the Assignment & Configuration File with the setacf Utility
Related Topics:
- Refer to the following sources for more information:
- Go to the Synplify User's Guide for details on how to assign properties.
- Go to "Resource Assignments in EDIF Input Files" and "Assigning Resources in a Third-Party Design Editor" in MAX+PLUS II Help for more information on assignments or properties that can be assigned when you use the Synplify software.
- Go to "resource assignments" or "ACF, format" in MAX+PLUS II Help using Search for Help on (Help menu) for information on entering assignments in the MAX+PLUS II software with Assign menu commands or in an ACF.
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