Using Synplicity Synplify & MAX+PLUS II Software

The following topics describe how to use the Synplicity Synplify software with MAX+PLUS^® II software. Click on one of the following topics for information:

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Setting Up the MAX+PLUS II/Synplicity Working Environment

Software Requirements
MAX+PLUS II Directory Structure
MAX+PLUS II/Synplicity Interface File Organization
Synplicity-Provided Logic Libraries

Design Flow

Design Entry

Design Entry Flow
VHDL
- Creating VHDL Designs for Use with MAX+PLUS II Software
- Entering Resource Assignments
  - Assigning Pins
  - Assigning the Implement in EAB Logic Option
  - Modifying the Assignment & Configuration File with the setacf Utility
Verilog HDL
- Creating Verilog HDL Designs for Use with MAX+PLUS II Software
- Entering Resource Assignments
  - Assigning Pins
  - Assigning the Implement in EAB Logic Option
  - Modifying the Assignment & Configuration File with the setacf Utility

Synthesis & Optimization

Synthesizing & Optimizing VHDL or Verilog HDL Files with Synplify Software
Analyzing VHDL or Verilog HDL Designs with the Synplify HDL Analyst

Compilation

Project Compilation Flow
Compiling Projects with MAX+PLUS II Software
- Synplicity Synplify-Specific Compiler Settings

Device Programming

Programming Altera Devices

Setting Up the MAX+PLUS II/Synplicity Working Environment

To use MAX+PLUS^® II software with Synplicity software, you must first install the MAX+PLUS II software, then establish an environment that facilitates entering and processing designs. The MAX+PLUS II/Synplicity interface is installed automatically when you install the MAX+PLUS II software on your computer. Ensure that you have correctly installed the MAX+PLUS II and Synplicity software versions described in the MAX+PLUS II/Synplicity Software Requirements.

You do not need to set any initialization or project variables before using Synplicity software with MAX+PLUS II software. Synplicity software features Direct Synthesis Technology that performs technology mapping directly to Altera^® device logic cells by inserting architecture-specific primitives to implement features such as logic cells, parallel expanders, carry chains, and cascade chains.

MAX+PLUS II/Synplicity Software Requirements

Table 1 shows the software applications that are used to generate, process, synthesize, and verify a project with MAX+PLUS^® II and Synplicity software:

Table 1. Software Requirements
Synplicity	Altera
version 3.0C1: Synplify HDL Analyst	MAX+PLUS II version 9.4

The MAX+PLUS II read.me file provides up-to-date information on which versions of Synplicity software applications are supported by the current version of MAX+PLUS II. It also provides information on installation and operating requirements. You should read the read.me file on the CD-ROM before installing the MAX+PLUS II software. After installation, you can open the read.me file from the MAX+PLUS II Help menu.

MAX+PLUS II Directory Structure (Synplicity Environment)

In the MAX+PLUS^® II software, a project name is the name of a top-level design file, without the filename extension. This design file can be an EDIF, Verilog HDL, or VHDL netlist file; an AHDL Text Design File (TDF); or any other MAX+PLUS II-supported design file. You can use a standard EDA tool to create an EDIF netlist file and import it into MAX+PLUS II software as an EDIF Input File (.edf).

Project design files and output files are stored in the project directory, with the exception of standard library functions provided by Altera or another EDA tool vendor. The MAX+PLUS II software stores the connectivity data on the links between design files in a hierarchical project in a Hierarchy Interconnect File (.hif) in the project directory, but refers to the entire project only by its project name. The MAX+PLUS II Compiler uses the HIF to build a single, fully flattened project database that integrates all the design files in a project hierarchy.

MAX+PLUS II/Synplicity Interface File Organization

Table 1 shows the MAX+PLUS^® II/Synplicity interface subdirectories that are created in the MAX+PLUS II system directory (by default, the /usr/maxplus2 directory) during MAX+PLUS II installation. For information on the other directories that are created during MAX+PLUS II installation, see "MAX+PLUS II File Organization" in MAX+PLUS II Installation in the MAX+PLUS II Getting Started manual.

Table 1. MAX+PLUS II Directory Organization
Directory	Description
./lmf	Contains the Altera-provided Library Mapping File, synplcty.lmf, which maps Synplicity logic functions to equivalent MAX+PLUS II logic functions.

Synplicity-Provided Logic Libraries

Synplicity software provides the altera logic library that is used for synthesizing and compiling VHDL and Verilog HDL designs. The altera library includes the following library files:

Library:	Description:
altera.vhd	A VHDL logic function library that includes the `LCELL`, `SOFT`, `GLOBAL`, `CASCADE`, and `CARRY` primitives for controlling design synthesis and fitting. These primitives can be instantiated directly in your VHDL file. These models allow you to perform functional VHDL simulation while maintaining an architecture-independent VHDL description.
altera.v	A Verilog HDL logic function library equivalent to the altera.vhd library file.

You can create your own libraries of custom logic functions for use with Synplicity software. You can use custom logic functions to incorporate an EDIF Input File, Text Design File (.tdf), or any other MAX+PLUS^® II-supported design file into a project. The MAX+PLUS II software uses the synplcty.lmf Library Mapping File to map standard Synplicity logic functions to equivalent MAX+PLUS II logic functions. To use custom logic functions, you can create a custom LMF that maps your custom logic functions to the equivalent EDIF Input File, Text Design File (.tdf), or other design file. Go to "Library Mapping File" in MAX+PLUS II Help for more information.

Synplicity Design Flow

Figure 1 shows the typical design flow for logic circuits created and processed with Synplicity and MAX+PLUS^® II software. Design Entry Flow, Project Compilation Flow, and Device Programming Flow show detailed diagrams of each stage of the design flow.

Figure 1. Design Flow between Synplicity & MAX+PLUS II Software

Synplicity Design Entry Flow

Figure 1 shows the design entry flow for the MAX+PLUS^® II/Synplicity interface.

Figure 1. MAX+PLUS II/Synplicity Design Entry Flow

Altera-provided items are shown in blue.

Creating VHDL Designs for Use with MAX+PLUS II Software

You can create VHDL design files with the MAX+PLUS^® II Text Editor or another standard text editor and save them in the appropriate directory for your project. The MAX+PLUS II Text Editor offers the following advantages:

VHDL templates are available with the VHDL Templates command (Templates menu). These templates are also available in the ASCII vhdl.tmp file, which is located in the /usr/maxplus2 directory.
If you use the MAX+PLUS II Text Editor to create your VHDL design, you can use the Syntax Coloring command (Options menu). The Syntax Coloring feature displays keywords and other elements of text in text files in different colors to distinguish them from other forms of syntax.

To create a VHDL design and convert it to an EDIF netlist file for use with MAX+PLUS II software, follow these steps:

Be sure to set up your working environment correctly, as described in Setting Up the MAX+PLUS II/Synplicity Working Environment.
Instantiate any MAX+PLUS II-supported logic function in your VHDL design. You can enter the following functions:
- Parameterized and non-parameterized megafunctions. MAX+PLUS II software also supports all functions in the library of parameterized modules (LPM) 2.1.0, except the truth table, finite state machine, and pad functions.
- Macrofunctions, including 74-series functions.
- Buffer primitives, including lcell, soft, global, carry, and cascade. The Synplicity altera.vhd library provides synthesis support for these functions.
- MegaCore™ functions offered by Altera or by members of the Altera Megafunction Partners Program (AMPP™). The OpenCore™ feature in the MAX+PLUS II software allows you to instantiate, compile, and simulate MegaCore functions before deciding whether to purchase a license for full device programming and post-compilation simulation support.
Choose Primitives, Old-Style Macrofunctions, and Megafunctions/LPM from the MAX+PLUS II Help menu for information on all MAX+PLUS II-supported functions.
If your design uses functions from the altera.vhd library, add the following Library and Use clauses to the top of a file that instantiates the macrofunction(s):

library altera; use altera.maxplus2.all;
For each MAX+PLUS II-supported logic function, include a black_box synthesis directive. See Figure 1. You can omit this step for functions from the altera.vhd library.

For any parameterized function, declare all parameters used in the function, their types, and their values. Attribute Declarations are used to declare the black_box attribute and the name and type of each parameter. The black_box attribute has the boolean type; refer to MAX+PLUS II Help for information on whether a parameter is of integer or string type. Attribute Specifications then assign values to each parameter. Figure 1 shows a VHDL design file that instantiates the lpm_ram_dq function.

Figure 1. VHDL Design File with LPM Function Instantiation

entity myram is 
port (clock, we: in bit;
      data : in bit_vector (3 downto 0);
      address: in bit_vector (1 downto 0);
      q: out bit_vector (3 downto 0));
end myram;

architecture arch1 of myram is

    -- Declare the component

    component myram_4x4
              port (data: in bit_vector (3 downto 0);
                       address: in bit_vector (1 downto 0);
                       inclock, outclock, we: in bit;
                       q: out bit_vector (3 downto 0) );
    end component;

--  Declare the black_box and parameters and their types

attribute black_box: boolean;
attribute LPM_WIDTH: integer;
attribute LPM_WIDTHAD: integer;
attribute LPM_TYPE: string;


-- Assign values to each attribute

attribute black_box of myram_4x4: component is true;
attribute LPM_WIDTH of myram_4x4: component is 4;
attribute LPM_WIDTHAD of myram_4x4: component is 2; 
-- Specify the name of the LPM function as the value of the 
-- LPM_TYPE attribute
attribute LPM_TYPE of myram_4x4: component is "LPM_RAM_DQ";

begin
          -- Instantiate the LPM component
          u1: myram_4x4  port map(data, address, clock,
		                                         clock, we, q); 

end arch1;

(Optional) Enter resource assignments for your VHDL design, as described in Entering Resource Assignments.
After you have completed your VHDL design, synthesize and optimize it with Synplify software, as described in Synthesizing & Optimizing VHDL or Verilog HDL Files with Synplify Software.

Entering Resource Assignments

The MAX+PLUS^® II software allows you to enter a variety of resource and device assignments for your projects. Resource assignments are used to assign logic functions to a particular pin, logic cell, I/O cell, embedded cell, row, column, Logic Array Block (LAB), Embedded Array Block (EAB), chip, clique, local routing, logic option, timing requirement, or connected pin group. In MAX+PLUS II software, you can enter all types of resource and device assignments with Assign menu commands. You can also enter pin, logic cell, I/O cell, embedded cell, LAB, EAB, row, and column assignments in the MAX+PLUS II Floorplan Editor. The Assign menu commands and the Floorplan Editor all save assignment information in the ASCII Assignment & Configuration File (.acf) for the project. In addition, you can edit ACFs manually in any standard text editor or with the setacf utility.

VHDL & Verilog HDL Design Files

When you use Synplicity Synplify software, you can assign a limited subset of these resource assignments by specifying attributes in the Synplify Design Constraints File (.sdc) or in the VHDL or Verilog HDL design files. The Synplify software automatically incorporates these attributes into the EDIF netlist file(s) generated from the HDL design files. MAX+PLUS II then automatically converts assignment information from the EDIF Input File into the ACF format. The following topics describe how to make MAX+PLUS II-compatible resource assignments before design processing with the Synplify software:

Assigning Pins
Assigning the Implement in EAB Logic Option
Modifying the Assignment & Configuration File with the setacf Utility

Assigning Pins

You can assign a single port to a specific pin to ensure that the signal is always associated with that pin, regardless of future changes to the project. You can specify pins in VHDL or Verilog HDL designs, or in a Synplify Design Constraints File (.sdc). If you add timing constraints or resource assignments in a separate Synplify Design Constraints File (.sdc), you must add the Synplify Design Constraints File (.sdc) to the project by adding it to the Source Files list in the Synplify window.

If your design uses resource assignment attributes that you wish to pass to the MAX+PLUS^® II software, you should save your file in EDIF netlist file format. See Entering Resource Assignments for more information.

VHDL Syntax

Use the following syntax to assign a pin in VHDL:

attribute altera_chip_pin_lc : string;
attribute altera_chip_pin_lc of <port name> : signal is "@<pin number(s)>";

Example:

attribute altera_chip_pin_lc : string;
attribute altera_chip_pin_lc of result : signal is 
	"@17, @166, @191, @152, @15, @148, @147, @149";

Verilog HDL Syntax

Use the following syntax to assign a pin in Verilog HDL:

<port name> /* synthesis altera_chip_pin_lc="@<pin number(s)>" */;

Example:

output [7:0] sum /* synthesis altera_chip_pin_lc="@17, @166, @191, @152, \ 
	@15, @148, @147, @149" */;

Synplify Design Constraints File Syntax

Use the following syntax to assign a pin in a Synplify Design Constraints file:

define_attribute <port name> altera_chip_pin_lc "@<pin number>"

Example:

define_attribute {DATA0[7:0]} altera_chip_pin_lc "@115,@116,@117,
@118,@119,@120,@121,@122"

Assigning the Implement in EAB Logic Option

You can assign the Implement in EAB logic option to individual logic functions in a FLEX^® 10K design. This option directs the MAX+PLUS^® II Compiler's Logic Synthesizer module to implement the function in an embedded array block (EAB) rather than in logic cell(s). You can specify the Implement in EAB Logic Option in VHDL or Verilog HDL designs, or in a Synplify Design Constraints File (.sdc). If you add timing constraints or resource assignments in a separate Synplify Design Constraints File (.sdc), you must add the Synplify Design Constraints File (.sdc) to the project by adding it to the Source Files list in the Synplify window.

If your design uses resource assignment attributes that you wish to pass to the MAX+PLUS II software, you should save your file in EDIF netlist file format. See Entering Resource Assignments for more information.

VHDL Syntax

Use the following syntax to assign the Implement in EAB logic option in VHDL:

attribute altera_implement_in_eab : boolean;
attribute altera_implement_in_eab of <port name>: label is true;

Example:

attribute altera_implement_in_eab of U1: label is true;
    begin    
        U1: mymux port map (in1 => a, sel => s, dout => o);

Verilog HDL Syntax

Use the following syntax to assign the Implement in EAB logic option in Verilog HDL:

<module or architecture name> /* synthesis altera_implement_in_eab=1 */;

Example:

sqrtb sq (.z(sqa), .a(a))  /* synthesis altera_implement_in_eab=1 */;
defparam sq.asize = 8;

Synplify Design Constraints File Syntax

Use the following syntax to assign the Implement in EAB logic option in a Synplify Design Constraints File (.sdc):

define_attribute {<module or architecture name>} altera_implement_in_eab 1

Example:

define_attribute {inst1.sqrt8} altera_implement_in_eab 1

Modifying the Assignment & Configuration File with the setacf Utility

Altera provides the setacf utility to help you modify a project's Assignment & Configuration File (.acf) from the command line, without opening the file with a text editor. Type setacf -h at a UNIX or DOS prompt to get help on this utility.

Creating Verilog HDL Designs for Use with MAX+PLUS II Software

You can create Verilog HDL design files with the MAX+PLUS^® II Text Editor or another standard text editor and save them in the appropriate directory for your project. The MAX+PLUS II Text Editor offers the following advantages:

Verilog HDL templates are available with the Verilog Templates command (Templates menu). These templates are also available in the ASCII verilog.tmp file, which is located in the /usr/maxplus2 directory.
If you use the MAX+PLUS II Text Editor to create your Verilog HDL design, you can use the Syntax Coloring command (Options menu). The Syntax Coloring feature displays keywords and other elements of text in text files in different colors to distinguish them from other forms of syntax.

To create a Verilog HDL design and convert it to an EDIF netlist file for use with MAX+PLUS II software, follow these steps:

Be sure to set up your working environment correctly, as described in Setting Up the MAX+PLUS II/Synplicity Working Environment.
Instantiate any MAX+PLUS II-supported logic function in your Verilog HDL design. You can enter the following functions:
- Parameterized and non-parameterized megafunctions. MAX+PLUS II software also supports all functions in the library of parameterized modules (LPM) 2.1.0, except the truth table, finite state machine, and pad functions.
- Macrofunctions, including 74-series functions.
- Buffer primitives, including lcell, soft, global, carry, and cascade. The Synplicity altera.v library provides synthesis support for these functions.
- MegaCore™ functions offered by Altera or by members of the Altera Megafunction Partners Program (AMPP™). The OpenCore™ feature in the MAX+PLUS II software allows you to instantiate, compile, and simulate MegaCore functions before deciding whether to purchase a license for full device programming and post-compilation simulation support.
Choose Primitives, Old-Style Macrofunctions, and Megafunctions/LPM from the MAX+PLUS II Help menu for information on all MAX+PLUS II-supported functions.
If your design uses functions from the altera.v library, add the library file name to the top of the Source Files list in the Synplify window.
For each MAX+PLUS II-supported logic function, include a black_box synthesis directive. You can omit this step for functions from the altera.v library.
For any parameterized function, you must declare all parameters used in the function, and their values. Figure 1 shows a Verilog HDL file that instantiates the lpm_ram_dq function. A comment in the Module Declaration contains the synthesis black_box directive and parameter names and values. This comment must immediately follow the port list and precede the closing semicolon (;). When you instantiate an LPM function, the LPM function name must be specified as the value of the LPM_TYPE parameter. In addition, each parameter must be listed on a separate line. See Figure 1.

Figure 1. Verilog HDL Design File with LPM Function Instantiation
```
// Define the black box
module myram_64x16 (data, address, inclock, outclock, we, q)
/* synthesis black_box 

                   LPM_WIDTH=16 
                   LPM_WIDTHAD=6 
                   LPM_TYPE="LPM_RAM_DQ"  */ ; 

input [15:0] data;
input [5:0] address;
input inclock, outclock;
input we;
output [15:0] q;

endmodule

// Instantiate the LPM parameterized module in the 
//    higher-level module myram
module myram(clock, we, data, address, q);
input clock, we;
input [15:0] data;
input [5:0] address;
output [15:0] q;


       myram_64x16 inst1 (data, address, clock, clock, we, q);

endmodule
```
(Optional) Enter resource assignments for your Verilog HDL design, as described in Entering Resource Assignments.
After you have completed your Verilog HDL design, synthesize and optimize it with Synplify software, as described in Synthesizing & Optimizing VHDL or Verilog HDL Files with Synplify Software.

Entering Resource Assignments

VHDL & Verilog HDL Design Files

Assigning Pins
Assigning the Implement in EAB Logic Option
Modifying the Assignment & Configuration File with the setacf Utility

Assigning Pins

VHDL Syntax

Use the following syntax to assign a pin in VHDL:

attribute altera_chip_pin_lc : string;
attribute altera_chip_pin_lc of <port name> : signal is "@<pin number(s)>";

Example:

attribute altera_chip_pin_lc : string;
attribute altera_chip_pin_lc of result : signal is 
	"@17, @166, @191, @152, @15, @148, @147, @149";

Verilog HDL Syntax

Use the following syntax to assign a pin in Verilog HDL:

<port name> /* synthesis altera_chip_pin_lc="@<pin number(s)>" */;

Example:

output [7:0] sum /* synthesis altera_chip_pin_lc="@17, @166, @191, @152, \ 
	@15, @148, @147, @149" */;

Synplify Design Constraints File Syntax

Use the following syntax to assign a pin in a Synplify Design Constraints file:

define_attribute <port name> altera_chip_pin_lc "@<pin number>"

Example:

define_attribute {DATA0[7:0]} altera_chip_pin_lc "@115,@116,@117,
@118,@119,@120,@121,@122"

Assigning the Implement in EAB Logic Option

VHDL Syntax

Use the following syntax to assign the Implement in EAB logic option in VHDL:

attribute altera_implement_in_eab : boolean;
attribute altera_implement_in_eab of <port name>: label is true;

Example:

attribute altera_implement_in_eab of U1: label is true;
    begin    
        U1: mymux port map (in1 => a, sel => s, dout => o);

Verilog HDL Syntax

Use the following syntax to assign the Implement in EAB logic option in Verilog HDL:

<module or architecture name> /* synthesis altera_implement_in_eab=1 */;

Example:

sqrtb sq (.z(sqa), .a(a))  /* synthesis altera_implement_in_eab=1 */;
defparam sq.asize = 8;

Synplify Design Constraints File Syntax

Use the following syntax to assign the Implement in EAB logic option in a Synplify Design Constraints File (.sdc):

define_attribute {<module or architecture name>} altera_implement_in_eab 1

Example:

define_attribute {inst1.sqrt8} altera_implement_in_eab 1

Modifying the Assignment & Configuration File with the setacf Utility

Synthesizing & Optimizing VHDL or Verilog HDL Files with Synplify Software

You can create and process VHDL or Verilog HDL files and convert them to Altera^® Hardware Description Language (AHDL) Text Design Files (.tdf) or EDIF Input Files (.edf) that can be processed by the MAX+PLUS^® II Compiler. The MAX+PLUS II Compiler can process a VHDL or Verilog HDL file that has been synthesized by Synplify software, saved as an AHDL TDF or an EDIF netlist file, and imported into the MAX+PLUS II software. The information presented here describes only how to use VHDL or Verilog HDL files that have been processed by Synplify software. For information on direct MAX+PLUS II support for VHDL or Verilog HDL Design Files, go to MAX+PLUS II VHDL or Verilog HDL Help.

To process a VHDL or Verilog HDL file with Synplify software for use with MAX+PLUS II software, follow these steps:

Be sure to set up your working environment correctly, as described in Setting Up the MAX+PLUS II/Synplicity Working Environment.
Create a VHDL file, <design name>.vhd, or a Verilog HDL file, <design name>.v, using the MAX+PLUS II Text Editor or another standard text editor and save it in a working directory. Go to Creating VHDL Designs for Use with MAX+PLUS II Software or Creating Verilog HDL Designs for Use with MAX+PLUS II Software for more information on HDL design entry.
Start the Synplify software:

On a UNIX workstation, type synplify at a UNIX prompt from your working directory.

or:

On a PC, double-click the synplify.exe icon in your \synplicity\bin directory.
Create a new project:
1. Choose New (File menu) to display the New dialog box, then select Project from the list. Choose OK.
2. Choose the Add button from the Project window. The Add Source Files dialog box is displayed.
3. Select your design file(s) and choose the Open button to add the file(s) to your Source Files list in the Synplify window.
If you wish to create a hierarchical project, make sure the top-level design file is at the bottom of the Source Files list by selecting the file and dragging it to the bottom of the list.

Select the target Altera device:

Choose the Change button in the Target section. The Set Device Option dialog box is displayed.
Select an Altera MAX^® (which includes Classic^™) or FLEX^® device family from the Technology list.
Select a device from the Part list.

(Optional) Turn on the Map logic cells to LCELLs option to increase performance. However, turning on this option may decrease area optimization.

For MAX or Classic designs, specify the following options:

Enter an appropriate value for the Percent of design to optimize for timing box.
Enter an appropriate value for the Maximum cell fan-in box.
(Optional) Turn on the Make Non-critical Cells Soft option to allow the MAX+PLUS II software to reduce the number of logic cells used in implementing non-timing critical portions of the design.

or:

For FLEX designs, select an appropriate value from the Speed Grade list.

Select EDIF or AHDL in the Result Format box to specify the output file format from the Synplify software. Choose OK.

Saving your project in AHDL TDF format may improve compilation time. However, if your design uses resource assignment attributes, you should save your file in EDIF netlist file format. See Entering Resource Assignments for more information.

Enter the frequency value for the project in the Frequency (MHz) box in the Synplify window.
(Optional) Turn on the Symbolic FSM Compiler option in the Synplify window to direct the Synplify software to automatically find and re-encode state machines in your design. Turning this option on may reduce unnecessary states and transitional logic.
Run the Synplify software by choosing the Run button in the Synplify window. Synplify software synthesizes and optimizes the design, and creates the EDIF netlist file <design name>.edf or the AHDL TDF <design name>.tdf.
(Optional) Run the HDL Analyst to analyze and evaluate the performance of your design, as described in Analyzing VHDL or Verilog HDL Designs with the Synplify HDL Analyst.
(Optional) Add appropriate timing constraints in a separate Synplify Design Constraints File (.sdc) or in the VHDL or Verilog HDL source file. If you add timing constraints or resource assignments in a separate .sdc file, you must add the .sdc file to the Source Files list in the Synplify window.
Correct any errors or warnings.
If you have corrected errors or warnings, or added timing constraints to your project, repeat step 8 to implement the changes in your synthesized design.
Create the /<project directory>/max2 subdirectory.
Copy the <design name>.edf or <design name>.tdf generated in step 8 to the /<project directory>/max2 directory.
Process your design with the MAX+PLUS II Compiler, as described in Compiling Projects with MAX+PLUS II Software.

Analyzing VHDL or Verilog HDL Designs with the Synplify HDL Analyst

You can use the optional Synplify HDL Analyst to analyze and evaluate the performance of your design graphically. The Synplify HDL Analyst instantly generates Register Transfer Level (RTL) schematics, as well as technology-mapped, gate-level schematics. You can instantly identify and fix potential problems earlier in the design cycle by cross-probing between the RTL schematics, gate-level schematics, and HDL source code. The Synplify HDL Analyst also highlights critical paths within the design to show which signals require optimization for performance. After you determine the critical speed paths, you can add timing constraints either to the VHDL or Verilog HDL source file or to a separate Synplify Design Constraints File (.sdc) to improve design performance.

To use the Synplify HDL Analyst after synthesizing your design with Synplify software, go through the following steps:

Be sure to set up your working environment correctly, as described in Setting Up the MAX+PLUS^® II/Synplicity Working Environment.
Create a VHDL or Verilog HDL design and save it in your working directory, as described in Creating VHDL Designs for Use with MAX+PLUS II Software or Creating Verilog HDL Designs for Use with MAX+PLUS II Software.
Synthesize and optimize your VHDL or Verilog HDL design with Synplify software, as described in Synthesizing & Optimizing VHDL or Verilog HDL Files with Synplify Software.

Choose an HDL Analyst view:

Choose RTL View (HDL_Analyst menu) to view the RTL schematic. When you select this view, the HDL Analyst displays a graphical representation of the design and the mouse pointer becomes a plus (+) symbol.

or:

Choose Technology View (HDL_Analyst menu) to view the gate-level schematic. When you select this view, the HDL Analyst displays a graphical representation of the design and the mouse pointer becomes a plus (+) symbol.

In either the RTL or Technology View, perform one or more of the following actions:
- Double-click the plus (+) symbol pointer on a port name or symbol to cross-probe your VHDL or Verilog HDL source design files.
  
  Because Synplify combines the a + b and a - b operations, cross-probing will highlight the Case Statement that defines both functions.
- Choose Find (HDL_Analyst menu) to select specific signals quickly in your design.
- Choose Show Critical Path (HDL_Analyst menu) to highlight the critical paths in the design.
- Select Filter Schematic (HDL_Analyst menu) to show only the nodes you have selected.
If necessary, correct the design and repeat the steps described in Synthesizing & Optimizing VHDL or Verilog HDL Files with Synplify Software.
Process your design with the MAX+PLUS II Compiler, as described in Compiling Projects with MAX+PLUS II Software.

Compiling Projects with MAX+PLUS II Software

The MAX+PLUS^® II Compiler can process design files in a variety of formats. This topic describes how to use MAX+PLUS II software to compile projects in which the top-level design file is an EDIF Input File (with the extension .edf).

	Refer to the following sources for additional information:
	Go to MAX+PLUS II Help for information on compiling VHDL and Verilog HDL, design files directly with the MAX+PLUS II Compiler. Go to Running Synopsys Compilers from MAX+PLUS II Software for information on running the Synopsys Design Compiler or FPGA Compiler software on a VHDL or Verilog HDL design from within the MAX+PLUS II Compiler window.

To compile a design (also called a "project") with MAX+PLUS II software, go through the following steps:

Create design files that are compatible with the MAX+PLUS II software and convert them into EDIF Input Files with the extension .edf. Specific instructions for some tools are described in these MAX+PLUS II ACCESS^SM Key Guidelines. Otherwise, refer to MAX+PLUS II Help or the product documentation for your design entry or synthesis and optimization tool.
If your design files contain symbols (or HDL instantiations) representing your own custom lower-level logic functions, create a mapping for each function in a Library Mapping File (.lmf) to map the custom symbol to the corresponding EDIF Input File, AHDL Text Design File (.tdf), or other MAX+PLUS II-supported design file. These custom functions are represented in design files as hollow-body symbols or "black box" HDL descriptions.

Go to "Library Mapping Files (.lmf)" in MAX+PLUS II Help for more information.

Open MAX+PLUS II and specify the name of your top-level design file as the project name with the Project Name command (File menu). If you open an HDL file in the MAX+PLUS II Text Editor, you can choose the Project Set Project to Current File command (File menu) instead.

You can also compile a project from a command line. However, the first time you compile a project, the settings you need to specify are easier to specify from within the MAX+PLUS II software. After you have run the graphical user interface for the MAX+PLUS II software at least once, you can more easily use the command-line setacf utility to modify options in the Assignment & Configuration File (.acf) for the project. Type setacf -h and maxplus2 -h for descriptions of setacf and MAX+PLUS II command-line syntax.

Choose Device (Assign menu) and select the target Altera device family in the Device Family drop-down list box. If you wish to implement the design logic in a specific device, select it in the Devices box. Otherwise, select AUTO to allow the MAX+PLUS II Compiler to choose the best device(s) in the current device family. If your design entry or synthesis and optimization tool required you to specify a target family and/or device, specify the same information in this dialog box. For information on partitioning logic among multiple devices, go to MAX+PLUS II Help. Choose OK.

Open the Compiler window by choosing the Compiler command (MAX+PLUS II menu). Go through the following steps to specify the options necessary to compile the design file(s) in your project:

Ensure that all EDIF netlist files have the extension .edf and choose EDIF Netlist Reader Settings (Interfaces menu).

Select a vendor name in the Vendor drop-down list box to activate the default settings for that vendor. This name should be the name of the vendor whose tool(s) you used to create the EDIF netlist files. If your vendor name does not appear, select Custom instead.

If you are compiling a design created with Synopsys FPGA Express software, select Synopsys, choose the Customize button, enter <project name>.lmf in the LMF #1 box, choose OK, and skip to step 6.

If you selected an existing vendor name in the Vendor box and your project contains design files that require custom LMF mappings, choose the Customize button to expand the dialog box to show all settings. Turn on the LMF #2 checkbox and type your custom LMF's filename in the corresponding text box, or select a name from the Files box. The selection in the Vendor box will change to Custom and all settings will be retained until you change them again.
If you selected Custom in the Vendor box, choose the Customize button to expand the dialog box to show all settings. Any previously defined custom settings will be displayed. Under Signal Names, type one or more names with up to 20 total name characters in the VCC or GND box if your EDIF Input File(s) use one or more names other than VCC or GND for the global high or low signals. Multiple signal names must be separated by either a comma (,) or a space. Under Library Mapping Files, turn on the LMF #1 checkbox and type a filename in the text box following it, or select a name from the Files box. If necessary, specify another LMF name in the LMF #2 box. Go to MAX+PLUS II Help for detailed information on the settings available in the EDIF Netlist Reader Settings dialog box.
Choose OK.

If your design files contain symbols (or HDL instantiations) representing your own custom lower-level logic functions, you may need to ensure that all files are present in your project directory, i.e., the same directory as the top-level design file. Otherwise, you must specify the directories containing these files as user libraries with the User Libraries command (Options menu).
Follow all guidelines that apply to your design entry or synthesis and optimization tool:
- Exemplar Logic Galileo Extreme-Specific Compiler Settings
- Synopsys DesignWare-Specific Compiler Settings
- Converting Synopsys FPGA Compiler & Design Compiler Timing Constraints into MAX+PLUS II-Compatible Format with the syn2acf Utility
- Synplicity Synplify-Specific Compiler Settings
If you wish to generate EDIF, VHDL, or Verilog HDL output files for post-compilation simulation or timing analysis with another EDA tool, go through the following steps:
1. (Optional) Turn on the Optimize Timing SNF command (Processing menu) to reduce the size of the output file(s). Turning on this command can reduce the size of output netlists by up to 30%.
  
  This command does not create optimized timing SNFs on UNIX workstations. However, a non-optimized timing SNF provides the same functional and timing information as an optimized timing SNF.
2. If you wish to generate EDIF Output Files (.edo), go through these steps:
  1. Turn on the EDIF Netlist Writer command (Interfaces menu). Then choose the EDIF Netlist Writer Settings command (Interfaces menu).
  2. Select a vendor name in the Vendor drop-down list box to activate the default settings for that vendor and choose OK. If your vendor name does not appear, select Custom instead and specify the settings that are appropriate for your simulation or timing analysis tool. Go to MAX+PLUS II Help for detailed information on the options available in the EDIF Netlist Writer Settings dialog box.
  3. To generate an optional Standard Delay Format (SDF) Output File (.sdo), choose the Customize button to expand the dialog box to show all settings. Select one of the SDF Output File options under Write Delay Constructs To, and choose OK.
  The filenames of the EDIF Output File(s) and optional SDF Output File(s) are the same as the user-defined chip name(s) for the project; if no chip names exist, the Compiler assigns filenames that are based on the project name. For a multi-device project, the Compiler also generates a top-level EDIF Output File that is uniquely identified by "_t" appended to the project name. In addition, the Compiler automatically generates a VHDL Memory Model Output File, <project name>.vmo, when it generates an EDIF Output File that contains memory (RAM or ROM).
3. If you wish to generate VHDL Output Files (.vho), turn on the VHDL Netlist Writer command (Interfaces menu). Then choose VHDL Netlist Writer Settings command (Interfaces menu). Select VHDL Output File (.vho) or one of the SDF Output File options under Write Delay Constructs To, and choose OK. SDF ver. 2.1 files contain timing delay information that allows you to perform back-annotation simulation in VHDL with VITAL-compliant simulation libraries. The VHDL Output Files generated by the Compiler have the extension .vho, but are otherwise named in the same way as the EDIF Output Files described above.
4. If you wish to generate Verilog HDL Output Files (.vo), turn on the Verilog Netlist Writer command (Interfaces menu). Then choose Verilog Netlist Writer Settings command (Interfaces menu). Select Verilog Output File (.vo) or one of the SDF Output File options under Write Delay Constructs To, and choose OK. SDF Output Files contain timing delay information that allows you to perform back-annotation simulation in Verilog HDL. The Verilog Output Files generated by the Compiler have the extension .vo, but are otherwise named in the same way as the EDIF Output Files described above.
To run the MAX+PLUS II Compiler, choose the Project Save & Compile command (File menu) or choose the Start button in the Compiler window.

See step 3 for information on running MAX+PLUS II software from the command line.
Once you have compiled the project with the MAX+PLUS II Compiler, you can use the VHDL, Verilog HDL, or EDIF output file(s), and the optional SDF Output File(s) (.sdo) to perform timing analysis or timing simulation with another EDA tool. Specific instructions for some tools are described in these MAX+PLUS II ACCESS Key Guidelines. Otherwise, refer to MAX+PLUS II Help or the product documentation for your EDA tool.

The MAX+PLUS II Compiler also generates a Report File (.rpt), a Pin-Out File (.pin), and one or more of the following files for device programming or configuration:

JEDEC Files (.jed)
Programmer Object Files (.pof)
SRAM Object Files (.sof)
Hexadecimal (Intel-format) Files (.hex)
Tabular Text Files (.ttf)

Synplicity Synplify-Specific Compiler Settings

If you are using the MAX+PLUS^® II Compiler to compile a design that has been synthesized and optimized with Synplify software, go through the following additional compilation steps:

Choose Global Project Logic Synthesis (Assign menu) to open the Global Project Logic Synthesis dialog box.

Select the appropriate logic synthesis style under the Global Project Synthesis Style:

If you turned on the Map Logic to LCELLs option in the Synplify Set Device Options dialog box when synthesizing a FLEX^® device design with Synplify software, select WYSIWYG or Fast in the Global Project Synthesis Style box.

or:

If you did not turn on the Map Logic to LCELLs option in the Synplify Set Device Options dialog box when synthesizing your design with Synplify software, or if you are using a MAX^® or Classic^™ device, select Normal in the Global Project Synthesis Style box.

For FLEX devices, choose Define Synthesis Style to display the Define Synthesis Style dialog box. Choose Advanced Options to display the Advanced Options dialog box and turn off the NOT Gate Push-Back option. Choose OK twice to close the dialog box.
Choose OK to close the Global Project Logic Synthesis dialog box.
Continue with the steps necessary to compile your project, as described in Compiling Projects with MAX+PLUS II Software.

Programming Altera Devices

Once you have successfully compiled and simulated a project with the MAX+PLUS^® II software, you can program an Altera^® device and test it in the target circuit. Figure 1 shows the device programming flow for MAX+PLUS II software.

Figure 1. MAX+PLUS II Device Programming Flow

Altera-provided items are shown in blue.

You can program devices with Altera programming hardware and MAX+PLUS II Programmer software installed on a 486- or Pentium-based PC or a UNIX workstation, or with programming hardware and software available from other manufacturers. Table 1 shows the available Altera programming hardware options on PCs and UNIX workstations.

*Table 1. Altera Programming Hardware*
Programming Hardware Option	PCs	UNIX Work- stations	MAX® 3000A Devices	Classic® & MAX 5000 Devices	MAX 7000 & MAX 7000E Devices	MAX 7000A, MAX 7000AE, MAX 7000B, MAX 7000S MAX 9000 & MAX 9000A Devices	FLEX® 6000, FLEX 6000A, FLEX 8000, FLEX 10K, FLEX 10KA, FLEX 10KB, & FLEX 10KE Devices	In-System Programming/ Configuration
Logic Programmer card, PL-MPU Master Programming Unit, and device-specific adapters
BitBlaster™ Download Cable
ByteBlasterMV™ Download Cable
MasterBlaster™ Download Cable

If you wish to transfer programming files from a UNIX workstation to a PC over a network with File Transfer Protocol (FTP) or other similar transfer programs, be sure to select binary transfer mode.

Programming hardware from other manufacturers varies, but typically consists of a device connected to one of the serial ports on the workstation. Various vendors, such as Data I/O and BP Microsystems, supply hardware and software for programming Altera devices.

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Using Synplicity Synplify & MAX+PLUS II Software

Setting Up the MAX+PLUS II/Synplicity Working Environment

Design Flow

Design Entry

Design Entry Flow

VHDL

Verilog HDL

Synthesis & Optimization

Compilation

Device Programming

Related Topics:

Setting Up the MAX+PLUS II/Synplicity Working Environment

Related Topics:

MAX+PLUS II/Synplicity Software Requirements

MAX+PLUS II Directory Structure (Synplicity Environment)

MAX+PLUS II/Synplicity Interface File Organization

Related Topics:

Synplicity-Provided Logic Libraries

Synplicity Design Flow

Figure 1. Design Flow between Synplicity & MAX+PLUS II Software

Synplicity Design Entry Flow

Figure 1. MAX+PLUS II/Synplicity Design Entry Flow

Creating VHDL Designs for Use with MAX+PLUS II Software

Figure 1. VHDL Design File with LPM Function Instantiation

Related Topics:

Entering Resource Assignments

VHDL & Verilog HDL Design Files

Related Topics:

Assigning Pins

VHDL Syntax

Verilog HDL Syntax

Synplify Design Constraints File Syntax

Related Topics:

Assigning the Implement in EAB Logic Option

VHDL Syntax

Verilog HDL Syntax

Synplify Design Constraints File Syntax

Related Topics:

Modifying the Assignment & Configuration File with the setacf Utility

Creating Verilog HDL Designs for Use with MAX+PLUS II Software

Figure 1. Verilog HDL Design File with LPM Function Instantiation

Related Topics:

Entering Resource Assignments

VHDL & Verilog HDL Design Files

Related Topics:

Assigning Pins

VHDL Syntax

Verilog HDL Syntax

Synplify Design Constraints File Syntax

Related Topics:

Assigning the Implement in EAB Logic Option

VHDL Syntax

Verilog HDL Syntax

Synplify Design Constraints File Syntax

Related Topics:

Modifying the Assignment & Configuration File with the setacf Utility

Synthesizing & Optimizing VHDL or Verilog HDL Files with Synplify Software

Related Topics:

Analyzing VHDL or Verilog HDL Designs with the Synplify HDL Analyst

Compiling Projects with MAX+PLUS II Software

Related Topics:

Synplicity Synplify-Specific Compiler Settings

Related Topics:

Programming Altera Devices

Figure 1. MAX+PLUS II Device Programming Flow

Table 1. Altera Programming Hardware

Related Topics: