Using Synplicity Synplify & MAX+PLUS II Software

The following topics describe how to use the Synplicity Synplify software with MAX+PLUS^® II software. Choose one of the following topics for information:

Open a printable version of all topics listed on this page.

Setting Up the MAX+PLUS II/Synplicity Working Environment

• Software Requirements
• MAX+PLUS II Directory Structure
• MAX+PLUS II/Synplicity Interface File Organization
• Synplicity-Provided Logic Libraries

Design Flow

Design Entry

• Design Entry Flow

• VHDL

  • Creating VHDL Designs for Use with MAX+PLUS II Software
  • Entering Resource Assignments
    • Assigning Pins
    • Assigning the Implement in EAB Logic Option
    • Modifying the Assignment & Configuration File with the setacf Utility

• Verilog HDL

  • Creating Verilog HDL Designs for Use with MAX+PLUS II Software
  • Entering Resource Assignments
    • Assigning Pins
    • Assigning the Implement in EAB Logic Option
    • Modifying the Assignment & Configuration File with the setacf Utility

Synthesis & Optimization

• Synthesizing & Optimizing VHDL or Verilog HDL Files with Synplify Software
• Analyzing VHDL or Verilog HDL Designs with the Synplify HDL Analyst

Compilation

• Project Compilation Flow
• Compiling Projects with MAX+PLUS II Software
  • Synplicity Synplify-Specific Compiler Settings

Device Programming

• Programming Altera Devices

Related Links:

• Go to the following topics for additional information:
  • MAX+PLUS II Development Software
  • Altera Programming Hardware
  • Synplicity web site (http://www.synplicity.com)