Creating VHDL Designs for Use with MAX+PLUS II Software

You can create VHDL design files with the MAX+PLUS^® II Text Editor or another standard text editor and save them in the appropriate directory for your project. The MAX+PLUS II Text Editor offers the following advantages:

• VHDL templates are available with the VHDL Templates command (Templates menu). These templates are also available in the ASCII vhdl.tmp file, which is located in the /usr/maxplus2 directory.

• If you use the MAX+PLUS II Text Editor to create your VHDL design, you can use the Syntax Coloring command (Options menu). The Syntax Coloring feature displays keywords and other elements of text in text files in different colors to distinguish them from other forms of syntax.

To create a VHDL design and convert it to an EDIF netlist file for use with MAX+PLUS II software, follow these steps:

1. Be sure to set up your working environment correctly, as described in Setting Up the MAX+PLUS II/Synplicity Working Environment.

2. Instantiate any MAX+PLUS II-supported logic function in your VHDL design. You can enter the following functions:

   • Parameterized and non-parameterized megafunctions. MAX+PLUS II software also supports all functions in the library of parameterized modules (LPM) 2.1.0, except the truth table, finite state machine, and pad functions.

   • Macrofunctions, including 74-series functions.

   • Buffer primitives, including lcell, soft, global, carry, and cascade. The Synplicity altera.vhd library provides synthesis support for these functions.

   • MegaCore™ functions offered by Altera or by members of the Altera Megafunction Partners Program (AMPP™). The OpenCore™ feature in the MAX+PLUS II software allows you to instantiate, compile, and simulate MegaCore functions before deciding whether to purchase a license for full device programming and post-compilation simulation support.

   Choose Primitives, Old-Style Macrofunctions, and Megafunctions/LPM from the MAX+PLUS II Help menu for information on all MAX+PLUS II-supported functions.

3. If your design uses functions from the altera.vhd library, add the following Library and Use clauses to the top of a file that instantiates the macrofunction(s):

   library altera;
use altera.maxplus2.all;

4. For each MAX+PLUS II-supported logic function, include a black_box synthesis directive. See Figure 1. You can omit this step for functions from the altera.vhd library.

5. For any parameterized function, declare all parameters used in the function, their types, and their values. Attribute Declarations are used to declare the black_box attribute and the name and type of each parameter. The black_box attribute has the boolean type; refer to MAX+PLUS II Help for information on whether a parameter is of integer or string type. Attribute Specifications then assign values to each parameter. Figure 1 shows a VHDL design file that instantiates the lpm_ram_dq function.

   Figure 1. VHDL Design File with LPM Function Instantiation

   entity myram is 
   port (clock, we: in bit;
         data : in bit_vector (3 downto 0);
         address: in bit_vector (1 downto 0);
         q: out bit_vector (3 downto 0));
   end myram;
   
   architecture arch1 of myram is
   
       -- Declare the component
   
       component myram_4x4
                 port (data: in bit_vector (3 downto 0);
                          address: in bit_vector (1 downto 0);
                          inclock, outclock, we: in bit;
                          q: out bit_vector (3 downto 0) );
       end component;
   
   --  Declare the black_box and parameters and their types
   
   attribute black_box: boolean;
   attribute LPM_WIDTH: integer;
   attribute LPM_WIDTHAD: integer;
   attribute LPM_TYPE: string;
   
   
   -- Assign values to each attribute
   
   attribute black_box of myram_4x4: component is true;
   attribute LPM_WIDTH of myram_4x4: component is 4;
   attribute LPM_WIDTHAD of myram_4x4: component is 2; 
   -- Specify the name of the LPM function as the value of the 
   -- LPM_TYPE attribute
   attribute LPM_TYPE of myram_4x4: component is "LPM_RAM_DQ";
   
   begin
             -- Instantiate the LPM component
             u1: myram_4x4  port map(data, address, clock,
   		                                         clock, we, q); 
   
   end arch1;
   
   

6. (Optional) Enter resource assignments for your VHDL design, as described in Entering Resource Assignments.

7. After you have completed your VHDL design, synthesize and optimize it with Synplify software, as described in Synthesizing & Optimizing VHDL or Verilog HDL Files with Synplify Software.

Related Links:

• Go to Compiling Projects with MAX+PLUS II Software in these MAX+PLUS II ACCESS^SM Key topics for related information.

Feedback

Did this information help you?

If no, please log onto mySupport to file a technical request or enhancement.