Synthesizing & Optimizing VHDL or Verilog HDL Files with Synplify Software

You can create and process VHDL or Verilog HDL files and convert them to Altera^® Hardware Description Language (AHDL) Text Design Files (.tdf) or EDIF Input Files (.edf) that can be processed by the MAX+PLUS^® II Compiler. The MAX+PLUS II Compiler can process a VHDL or Verilog HDL file that has been synthesized by Synplify software, saved as an AHDL TDF or an EDIF netlist file, and imported into the MAX+PLUS II software. The information presented here describes only how to use VHDL or Verilog HDL files that have been processed by Synplify software. For information on direct MAX+PLUS II support for VHDL or Verilog HDL Design Files, go to MAX+PLUS II VHDL or Verilog HDL Help.

To process a VHDL or Verilog HDL file with Synplify software for use with MAX+PLUS II software, follow these steps:

1. Be sure to set up your working environment correctly, as described in Setting Up the MAX+PLUS II/Synplicity Working Environment.

2. Create a VHDL file, <design name>.vhd, or a Verilog HDL file, <design name>.v, using the MAX+PLUS II Text Editor or another standard text editor and save it in a working directory. Go to Creating VHDL Designs for Use with MAX+PLUS II Software or Creating Verilog HDL Designs for Use with MAX+PLUS II Software for more information on HDL design entry.

3. Start the Synplify software:

   On a UNIX workstation, type synplify at a UNIX prompt from your working directory.

   or:

   On a PC, double-click the synplify.exe icon in your ¥synplicity¥bin directory.

4. Create a new project:

   1. Choose New (File menu) to display the New dialog box, then select Project from the list. Choose OK.

   2. Choose the Add button from the Project window. The Add Source Files dialog box is displayed.

   3. Select your design file(s) and choose the Open button to add the file(s) to your Source Files list in the Synplify window.

   If you wish to create a hierarchical project, make sure the top-level design file is at the bottom of the Source Files list by selecting the file and dragging it to the bottom of the list.

5. Select the target Altera device:

   1. Choose the Change button in the Target section. The Set Device Option dialog box is displayed.

   2. Select an Altera MAX^® (which includes Classic^™) or FLEX^® device family from the Technology list.

   3. Select a device from the Part list.

   4. (Optional) Turn on the Map logic cells to LCELLs option to increase performance. However, turning on this option may decrease area optimization.

      For MAX or Classic designs, specify the following options: Enter an appropriate value for the Percent of design to optimize for timing box. Enter an appropriate value for the Maximum cell fan-in box. (Optional) Turn on the Make Non-critical Cells Soft option to allow the MAX+PLUS II software to reduce the number of logic cells used in implementing non-timing critical portions of the design.

      or:

      For FLEX designs, select an appropriate value from the Speed Grade list.

   5. Select EDIF or AHDL in the Result Format box to specify the output file format from the Synplify software. Choose OK.

   Saving your project in AHDL TDF format may improve compilation time. However, if your design uses resource assignment attributes, you should save your file in EDIF netlist file format. See Entering Resource Assignments for more information.

6. Enter the frequency value for the project in the Frequency (MHz) box in the Synplify window.

7. (Optional) Turn on the Symbolic FSM Compiler option in the Synplify window to direct the Synplify software to automatically find and re-encode state machines in your design. Turning this option on may reduce unnecessary states and transitional logic.

8. Run the Synplify software by choosing the Run button in the Synplify window. Synplify software synthesizes and optimizes the design, and creates the EDIF netlist file <design name>.edf or the AHDL TDF <design name>.tdf.

9. (Optional) Run the HDL Analyst to analyze and evaluate the performance of your design, as described in Analyzing VHDL or Verilog HDL Designs with the Synplify HDL Analyst.

10. (Optional) Add appropriate timing constraints in a separate Synplify Design Constraints File (.sdc) or in the VHDL or Verilog HDL source file. If you add timing constraints or resource assignments in a separate .sdc file, you must add the .sdc file to the Source Files list in the Synplify window.

11. Correct any errors or warnings.

12. If you have corrected errors or warnings, or added timing constraints to your project, repeat step 8 to implement the changes in your synthesized design.

13. Create the /<project directory>/max2 subdirectory.

14. Copy the <design name>.edf or <design name>.tdf generated in step 8 to the /<project directory>/max2 directory.

15. Process your design with the MAX+PLUS II Compiler, as described in Compiling Projects with MAX+PLUS II Software.

Related Links:

• Go to the following topics for additional information:
  • FLEX Devices
  • MAX Devices
  • Classic Device Family

---

Feedback

Did this information help you?

If no, please log onto mySupport to file a technical request or enhancement.

---

Altera does not warrant that this solution will work for the customer's intended purpose and disclaims all liability for use of or reliance on the solution.