Viewlogic Powerview Graphical User Interface & the Altera Toolbox

You use the Powerview graphical interface manager, the Cockpit, and the Altera^® Toolbox to start all Powerview and Altera tools. Within the Altera Toolbox, you can specify the Max2 Express Drawer or the Design Tools Drawer to work with the Altera/Viewlogic Powerview interface.

The Max2 Express Drawer provides a quick and seamless way to transfer designs created in Powerview to the MAX+PLUS^® II software for compilation, then return the compiled designs to Powerview for simulation and timing verification. Table 1 describes the Max2 Express Drawer tools.

Table 1. Max2 Express Drawer Tools
Tool	Description
max2_VDraw	Launches the Powerview ViewDraw schematic entry tool.
VHDL<->max2	Launches all tools necessary to synthesize a VHDL design, compile for an Altera device, and generate a .vsm file for simulation with the Powerview ViewSim simulator.
SCH<->max2	Launches all tools necessary to compile a schematic design entered with Powerview ViewDraw software for an Altera device and to generate a .vsm file for simulation with Powerview ViewSim and .edo, .sdo, and .vmo files for timing analysis with MOTIVE for Powerview.
max2_VSim	Launches the Powerview ViewSim simulator.
max2_VTrace	Launches the Powerview ViewTrace simulation waveform editor.
max2_MOTIVE	Launches the MOTIVE for Powerview ViewDraw static timing verification tool.

The Design Tools Drawer provides tools that enable you to create a design with the Powerview tools, compile the design in the MAX+PLUS II software, and simulate and verify the design with Powerview software. Table 2 describes the Design Tools Drawer tools.

Table 2. Design Tools Drawer Tools
Tool	Description
max2_VDraw	Launches the Powerview ViewDraw schematic entry tool.
max2_analyzer	Launches the Powerview VHDL Analyzer software.
max2_syn	Launches the Powerview VHDL synthesis tool.
max2_chk	Launches the Powerview schematic verification tool.
max2_vsmnet	Launches the Powerview vsm utility that converts a wirelist file into a .vsm file.
max2_VSim	Launches the Powerview ViewSim simulator.
max2_VTrace	Launches the Powerview ViewTrace simulator.
max2_edifo	Launches the Powerview EDIF netlist writer, edifneto.
max2_VGen	Launches the Powerview ViewGen utility that generates a schematic from a wirelist file.
max2	Launches the MAX+PLUS II Compiler.
max2_edifi	Launches the Powerview EDIF Netlist Reader, edifneti.
max2_vhdl2sym	Launches the Powerview vhdl2sym utility that generates a symbol from a VHDL file.
max2_VantgMgr	Launches the Powerview Vantage VHDL Library Manager tool.
max2_VantgAnlz	Launches the Vantage VHDL Analyzer software.
max2_VCS	Launches the Fusion/VCS Simulator.
max2_MOTIVE	Launches the MOTIVE for Powerview static timing verification tool.

---

Feedback

Did this information help you?

If no, please log onto mySupport to file a technical request or enhancement.

---

Altera does not warrant that this solution will work for the customer's intended purpose and disclaims all liability for use of or reliance on the solution.