MAX+PLUS II/Viewlogic Powerview Project File Structure
In the MAX+PLUS® II software, a project name is the name of a top-level design file, without the filename extension. This design file can be an EDIF, Verilog HDL, or VHDL netlist file; an Altera® Hardware Description Language (AHDL) TDF; or any other MAX+PLUS II-supported design file. The EDIF netlist file must be created by Powerview and imported into the MAX+PLUS II software as an EDIF Input File (.edf). Figure 1 shows an example of MAX+PLUS II project directory structure that includes Powerview-generated files.
Figure 1. Sample MAX+PLUS II Project Organization
The MAX+PLUS II software stores the connectivity data on the links between design files in a hierarchical project in a Hierarchy Interconnect File (.hif), but refers to the entire project only by its project name. The MAX+PLUS II Compiler uses the HIF to build a single, fully flattened project database that integrates all the design files in a project hierarchy.
Unlike Powerview, the MAX+PLUS II software does not automatically create a project directory when you create a project. A single directory can contain several MAX+PLUS II design files, and you can specify any one of the designs in the directory as a project in the MAX+PLUS II software.
Viewlogic Powerview Local Work Area Structure
When you create a project with the Powerview Cockpit's Create command (Project menu), the project directory is created. You should generate design files and functional simulation files under this directory. A max2 subdirectory is automatically created under your current project directory when you generate an EDIF file from your schematic or VHDL file. The <project name>.edf file is stored in the max2 subdirectory. All MAX+PLUS® II Compiler output files are created in the /<project name>/max2 subdirectory.
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ViewDraw files are identified by their directories and not by their extensions, so it is easy to overwrite files unintentionally. To avoid overwriting files, Altera recommends that you create a new project directory, <project name>/max2/sim, where you can generate all the files needed for simulation. |
ViewDraw Project File Structure
Each ViewDraw project directory contains three subdirectories: wir, sch, and sym. See Table 1.
| Table 1. ViewDraw Subdirectories |
| Directory |
Topics |
| ./wir |
Wirelist files that contain connectivity information for a particular logic block |
| ./sch |
Schematics that contain logic |
| ./sym |
Symbol files that are the ViewDraw graphical representation of the logic blocks |
Each file type uses the filename extension .1. Different file types are distinguished only by their directory: /lib/wir/<project name>.1 is a wirelist file; /lib/sch/<project name>.1 is the corresponding schematic file; and /lib/sym/<project name>.1 is the corresponding symbol.
VHDL Project File Structure
Each VHDL project directory contains three subdirectories. See Table 2.
| Table 2. VHDL Subdirectories |
| Directory |
Topics |
| ./synth |
All synthesis-related files and directories |
| ./synth/<entity> |
Four types of files: <entity>.pdf, <entity>.opt, <entity>.sta, and <entity>.gnl |
| ./wir |
Wirelist for synthesized VHDL modules |
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For each VHDL entity in the design, there is a corresponding ./synth/<entity> directory. |
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