The Quartus® II software incremental compilation feature is the most productive incremental design methodology for high-density FPGAs. It reduces compilation times by up to 70 percent while preserving the results of unchanged logic in your design. For additional information on incremental compilation, see:
To search for known incremental compilation issues and technical support solutions, use Altera’s Knowledge Database. You can also visit the Altera® Forum to discuss technical issues with other Altera users.
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Incremental compilation resources
Table 1 provides links to available documentation on incremental compilation.
| Table 1. Incremental Compilation Documentation | |
| Title | Description |
|---|---|
| Increasing Productivity with Quartus II Incremental Compilation (PDF) | This paper describes how an incremental compilation flow can improve your productivity when designing for high-density, high-performance FPGAs. |
| Design Planning with Quartus II Software (PDF) | This chapter of the Quartus II Handbook discusses important FPGA design planning issues, provides recommendations, and describes various tools available for use with Altera FPGAs to help you improve design productivity. It briefly describes how planning can improve your success with incremental compilation. |
| Quartus II Incremental Compilation for Hierarchical and Team-Based Design (PDF) |
This chapter of the Quartus II Handbook describes Quartus II software features and design methodologies for incremental compilation, and includes various recommended design flows and application examples to help you meet your design goals. This is the primary document for details about incremental compilation. |
| Best Practices for Incremental Compilation Partitions and Floorplan Assignments (PDF) | This chapter of the Quartus II Handbook provides a set of guidelines to help you partition your design to take advantage of Quartus II incremental compilation, and to help you create a design floorplan (using LogicLockTM regions) to support the flow. |
Table 2 provides links to available training and demonstrations on incremental compilation.
| Table 2. Incremental Compilation Training and Demonstrations | |
| Title | Description |
|---|---|
| Incremental Compilation and Team-Based Design Online Demonstration |
You will see a demonstration of the incremental compilation feature used in both top-down (single Quartus II project) and bottom-up (multiple-project) team-based compilation methodologies. This is a 10-minute online demonstration. |
| Introduction to Incremental Compilation Online Course |
You will learn how to preserve design performance and reduce compilation time by using the incremental compilation feature. By the end of this training, you will be able to use LogicLock regions in physical partitioning of your design. You will be able to segment your design into logical design partitions. You will be able to apply the incremental compilation methodology to both the top-down and bottom-up design flows. This is a 2.5-hour online course. |
| Design Partition Planner in the Quartus II Software Online Course |
The design partition planner allows you to see how your design blocks are inter-related and illustrate the data flow in your design. In this training, you will learn to use the design partition planner to make informed design partition choices and achieve better results. You will see a demonstration of the graphical interactive environment for creating and experimenting with partitions. This is a 1-hour online course. |
| The Quartus II Software Design Series: Optimization Instructor-Led Course |
You will learn advanced features of the Quartus II software that enable you to shorten your design cycle as well as improve your design performance and utilization. You will use the incremental compilation flow and LogicLock regions in the Quartus II software to reduce compilation times and preserve performance. This is a 1-day instructor-led course. |
