With today's time-to-market constraints, you must plan your FPGA I/O pins early in the design cycle. Quartus® II software has best-in-class I/O management tools for early I/O planning and sign-off. While planning your I/O pins, prepare your FPGA design for PCB integration. Create "board-aware" board trace models in Quartus II software to get I/O signal integrity metrics or generate IBIS/HSPICE models for simulation in third-party signal integrity simulation tools. Export the I/O pin-outs to create custom schematic symbols for use in popular schematic capture tools.
For additional information on I/O management, PCBs, and board-level signal integrity, see the following:
- I/O Management Documentation
- I/O Management Training and Demonstrations
- I/O Navigator
- Design Examples
- Pin-Out Files for Altera® Devices
- Pin Connection Guidelines
- BSDL Files for Altera Devices
- PCB Design Documentation
- PCB Design Resource and Training
- Capture CIS Symbols
- Board-Level Signal Integrity Documentation
- Signal Integrity Analysis Training
- Signal Integrity Technology Center
For a brief overview of the I/O features in Quartus II software, refer to the Quartus II software features page.
For further technical support, use mySupport to create, view, and update your service requests.
I/O Management Resources
Table 1 provides links to available documentation on I/O management. For details on I/O features and supported standards of Altera FPGAs, refer to the selectable I/O standards chapter in the appropriate device handbook.
|Table 1. I/O Management Documentation|
|I/O Management (PDF)||This chapter of the Quartus II Handbook discusses FPGA I/O planning flow, detailing how and when to use the many I/O planning tools such as pin planner. It describes how to create top-level HDL files using pin planner's early I/O planning flow with custom megafunctions. It describes the methodology for I/O assignments and analysis, and discusses advanced I/O timing analysis with board trace models in Quartus II software.|
|Simultaneous Switching Noise (SSN) Analysis and Optimization (PDF)||This chapter of the Quartus II Handbook explains how to use the new SSN analyzer and optimization tool in Quartus II software 9.0 and later. It discusses the tool flow and explains what is required to perform an accurate SSN analysis in your FPGA design. It also describes Quartus II software SSN optimization techniques and settings.|
|AN 90: SameFrame Pin-Out Design for FineLine BGA Packages (PDF)||Describes vertical and cross-package migration for Altera FLEX® and MAX® devices.|
Table 2 provides links to available training and demonstrations on I/O management.
|Table 2. I/O Management Training and Demonstrations|
|The Quartus II Software Design Series: Foundation (English) (Instructor-Led Course)
The Quartus II Software Design Series: Foundation
|You will learn how to use Quartus II software to develop an FPGA or CPLD. You will create a new project, enter new or existing design files, and compile and configure your device to see the design working in-system.
This is a 1-day instructor-led course.
This is an 8-hour online training.
|I/O Assignment Analysis||
See a quick demonstration on Quartus II software's I/O assignment tools.
This is a 4-minute online demonstration.
|I/O System Design
You will learn how to use the I/O management features found in Quartus® II software.
PCB Design Resources
Table 3 provides links to available documentation for third-party PCB tools.
|Table 3. PCB Design Documentation|
|Cadence Design Tools Support (PDF)||This chapter of the Quartus II Handbook describes the design flow between Quartus II software and Cadence PCB design tools.|
|Mentor Graphics PCB Design Tools Support (PDF)||This chapter of the Quartus II Handbook describes the design flow between Quartus II software and Mentor Graphics® design tools.|
|I/O Management (PDF)||This chapter of the Quartus II Handbook includes information about creating board trace models for use with the advanced I/O timing analysis in Quartus II software.|
|Power Distribution Network (PDN) Tool User Guide (PDF)||This user guide provides a brief overview of the various tabs in the PDN tool. You can quickly and accurately design a robust power delivery network by coming up with an optimum number of capacitors that meet the target impedance requirements for a given power supply.|
|High-Speed Board Design Advisor for PDN (PDF)||This document contains a step-by-step tutorial and checklist of best-practice guidelines to design and review a power distribution network (PDN).|
|AN 224: High-Speed Board Layout Guidelines (PDF)||Includes information and suggestions for designing and laying out high-speed boards with Altera FPGAs.|
|AN 75: High-Speed Board Designs (PDF)||Provides general information on high-speed board design.|
Table 4 provides a link to a tutorial for third-party PCB tools.
|Table 4. PCB Design Resources and Training|
|Power Distribution Network (PDN) Tool||This easy-to-use PDN design tool is a graphical tool used with all Altera FPGAs to optimize the board-level PDN.|
|Power Distribution Network Design Using Altera PDN Design Tools
|You will learn about the challenges involved with PDN design for high-speed devices and how to overcome them. Specifically, you will learn about the Altera PDN design tools available and how to use them.|
|Power Distribution Network Design for Stratix III and Stratix IV
You will learn about common power design challenges and solutions, power distribution network (PDN) and different decoupling schemes, and the methodology for Frequency Domain Target Impedance Method (FDTIM) decoupling.
Board-Level Signal Integrity Resources
Table 5 provides links to available resources for board-level signal integrity analysis.
|Table 5. Board-Level Signal Integrity Resources|
|Signal Integrity Analysis with Third-Party Tools (PDF)||This chapter of the Quartus II Handbook describes the methodology to perform signal integrity (SI) analysis using IBIS and HSPICE models of I/O pins with third-party SI simulation tools.|
|I/O Management (PDF)||This chapter of the Quartus II Handbook provides a section on advanced I/O timing analysis. Advanced I/O timing analysis requires board trace models for accurate representation of board traces in Quartus II software. The methodology of specifying board trace models and running advanced I/O timing analysis is explained. Some signal integrity metrics are also reported as part of advanced I/O timing analysis.|
Table 6 provides a link to a course for signal integrity analysis.
|Table 6. Signal Integrity Analysis|
|Advanced I/O System Design
|You will learn about the need for signal integrity simulation & analysis when designing high-speed PCBs. You will learn what simultaneous switching noise (SSN) is and the tools available to reduce or eliminate it.|