Generating IBIS Output Files with the Quartus II Software
You can generate an IBIS Output File (.ibs) in the Quartus II software to perform board-level signal integrity verification in other EDA tools.
Note: IBIS model generation is fully supported for all devices supported by the Quartus II software. For additional IBIS model device support and support files, refer to the "IBIS models" section of the Device Support section on the Altera website.
In the Board-Level Signal Integrity Analysis box, select IBIS from the Format list.
Type or browse to the location you want to use as the output directory for the IBIS Output File. The default location is <project directory>/board/ibis.
Turn on Enable model selector to list all the possible models for each I/O cell in the design.
To generate the IBIS Output File, compile the design.
Note: The EDA Netlist Writer places the IBIS Output File in the specified directory. If you have already compiled the design, and want to specify different EDA tools settings and generate output files without recompiling the design, on the Processing menu, point to Start and then click Start EDA Netlist Writer.
Use the IBIS Output File to perform board-level signal integrity verification in the Cadence Allegro PCB SI, the Mentor Graphics ICX Pro and HyperLynx, and the Zuken CADSTAR and CR-5000 Lightning software.
To generate an IBIS Output File that contains only reserved pins and configuration pins:
On the Assignments menu, click Settings.
In the Category list, select Board-Level under EDA Tool Settings.
In the Board-Level Signal Integrity Analysis box, select IBIS from the Format list.
Click Start I/O Assignment Analysis.
To generate the IBIS Output File, on the processing menu, click Start, and then click Start EDA Netlist Writer.
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