You access this command by pointing to EDA Simulation Tool, and then clicking Run EDA Timing Analysis Tool on the Tools menu.
Note: The Run EDA Timing Analysis Tool command is available only after you perform a full compilation on a project and you specify an EDA timing analysis tool. If you use this command after the design source files change, the EDA timing analysis tool runs the timing analysis with the data from the last compilation.
Allows you to run an EDA timing analysis tool from within the Quartus II software without recompiling the design. The Quartus II software uses a Tcl Script File (.tcl) to launch the EDA timing analysis tool and process the Quartus II–generated VHDL Output File (.vho) or Verilog Output File (.vo) for the design.
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