More EDA Tool Simulation Settings Dialog Box

You open this dialog box by clicking More Settings in the Simulation page of the Settings dialog box.

This dialog box allows you to specify simulation settings for third party EDA simulation tools.

Architecture name in VHDL output netlist:

Directs the EDA Netlist Writer to set the Architecture name in the VHDL simulation netlist with the name you type in the Setting box.

Scripting Information

Keyword: eda_vhdl_arch_name

Settings: <string>

Bring out device-wide set/reset signals as ports:

Directs the EDA Netlist Writer to add the devpor, devclrn, and devoe signals in the design as input ports in the top-level design hierarchy in the VHDL Output File (.vho) or Verilog Output File (.vo) output netlist for the project.

Scripting Information

Keyword: eda_write_device_control_ports

Settings: on | off

*default

Disable setup and hold violations detection in input registers of bi-directional pins:

Directs the EDA Netlist Writer to disable detection of setup and hold time violations for input registers of bi-directional pins.

Scripting Information

Keyword: eda_setup_hold_detection_input_registers_bidir_pins_disabled

Settings: on | off

*default

Do not write top level VHDL entitiy:

Directs the EDA Netlist Writer not to write the top-level entity definition into the VHDL file.

Scripting Information

Keyword: eda_writer_dont_write_top_entity

Settings: on | off

*default

Flatten buses into individual nodes:

Directs the EDA Netlist Writer to flatten all buses when creating VHDL Output Files (.vho). You should turn on this option if your EDA tool does not support buses.

Scripting Information

Keyword: eda_flatten_buses

Settings: on | off

*default

Generate netlist for functional simulation only:

Directs the Quartus II software to generate a VHDL Output File (.vho) or Verilog Output File (.vo) for functional simulation with other EDA simulation tools. A Standard Delay Format Output File (.sdo) is not generated for the project. You can compile a VHDL Output File or Verilog Output File as part of performing a functional simulation with the ModelSim or NCSim software.

Scripting Information

Keyword: eda_generate_functional_netlist

Settings: on | off

*default

Maintain hierarchy:

Directs the EDA Netlist Writer to maintain the original user design hierarchy when generating the VHDL Output File (.vho) or Verilog Output File (.vo) output netlist for the project.

Scripting Information

Keyword: eda_maintain_design_hierarchy

Settings: on | off

*default

Truncate long hierarchy paths:

Directs the EDA Netlist Writer to truncate hierarchical node names to 80 name characters..

Scripting Information

Keyword: eda_truncate_long_hierarchy_paths

Settings: on | off

*default