If you select a specific design entry or synthesis tool and want to have that tool automatically synthesize the design, turn on Run this tool automatically to synthesize the current design.
Specify the simulation tool settings:
In the Category list, select Simulation under EDA Tool Settings.
In the Tool name list, select the name of the simulation tool or select Custom.
To run a gate-level simulation automatically after compilation, turn on Run gate-level simulation automatically after compilation.
If necessary, specify HDL output settings for the selected simulation tool with the settings under EDA Netlist Writer Options.
If you selected the ModelSim, ModelSim-Altera, NCSim, VCS, or VCS MX software in the Tool name list, under NativeLink settings you can specify settings for running the simulation software with a test bench.
Note: If you select a specific EDA tool, the Compiler selects the default Verilog HDL output settings or VHDL output settings for that tool.
If you have previously defined customized settings, you can select Custom to use the customized settings.
If you are using the version of the ModelSim software installed as part of the Quartus II software, specify ModelSim-Altera as the simulation tool. If you are using the full version of the ModelSim software, specify ModelSim as the simulation tool.
The directory created by the Quartus II software during compilation is located in the simulation directory in the current project directory. This directory uses the name of the specified EDA simulation tool or custom if you specify Custom.
If you use the default <None> selection, no settings are defined, and no output files are generated.
Specify the timing analysis tool and Verilog or VHDL output settings:
In the Category list, select Timing Analysis under EDA Tool Settings.
In the Tool name list, select the name of the timing analysis tool.
In the Time scale list, select a time scale.
If you want to map illegal HDL characters, turn on Map illegal HDL characters.
If you want to truncate hierarchical node names to 80 characters or less, turn on Truncate long hierarchy paths.
If you want to flatten all buses when creating the Verilog Output File or VHDL Output File, turn on Flatten buses into individual nodes.
(UNIX workstations only) If you specified the Synopsys PrimeTime software as the timing analysis tool, you can specify settings for running the PrimeTime software in shell mode or GUI mode.
Note: If you select a specific EDA tool, the Compiler selects the default Verilog HDL output settings or VHDL output settings for that tool.
If you have previously defined customized settings, you can select Custom VHDL or Custom Verilog HDL to use the customized settings.
After you compile the design, a VHDL Output File or a Verilog Output File and a Standard Delay Format Output File are created and placed in a tool-specific directory. If you turned on Generate netlist for functional simulation only, an Standard Delay Format Output File is not created.
You can select Stamp (board model) in the Tool name list to perform timing verification on a board-level design and create the Stamp model files.
The directory created by the Quartus II software during compilation is located in the timing directory in the current project directory. This directory uses the name of the specified EDA simulation or timing analysis tool or custom if you specify Custom VHDL or Custom Verilog HDL.
If you use the default <None> selection, no settings will be defined, and no output files are generated.
Specify the output format for files used by board-level verification tools:
In the Category list, select Board-Level under EDA Tool Settings.
Select the Format and Output directory for the type of board-level verification tool you plan to use: symbol generation, signal integrity, or timing analysis.
Specify the formal verification tool:
In the Category list, select Formal verification under EDA Tool Settings.
Under Tool settings, in the Tool name list, select the name of the formal verification tool.
Specify the physical synthesis tool:
In the Category list, select Physical Synthesis under EDA Tool Settings.
Under Tool settings, in the Tool name list, select the physical synthesis tool. If you select the PALACE in the tool name list, specify the following settings:
Under Optimization effort, select the level of optimization.
Under Retiming, select the retiming level.
Under Physical synthesis, select the physical synthesis level.
If you want the Quartus II software to use the physical constraints generated by the physical synthesis tool during recompilation, turn on Use generated physical constraints in the Quartus II software.
Click OK.
(UNIX workstations only) To run an EDA design entry/synthesis, simulation, timing analysis, formal verification, or physical synthesis tool automatically from the Quartus II software with the NativeLink feature, you can specify the location of tools in the EDA Tool Options page of Options dialog box or use the Tcl command set_user_option to specify the location.
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