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Specifying EDA Tool Settings for Design Entry and Synthesis

To specify options for processing design files created by other EDA tools:

  1. On the Assignments menu, click Settings.

  2. In the Category list, select Design Entry and Synthesis under EDA Tool Settings.

  3. In the Tool name list, select the name of design entry or synthesis too, or select Custom to specify custom EDA tool input settings.

  4. In the Data Format box, enter the type of input file you are importing into the Quartus II software, which may include EDIF, Verilog HDL, VHDL, and AHDL, depending on the type of tool selected.

  5. If you selected EDIF in the Data Format list, you can specify non-default VCC or GND signal names. If you want to change these names, type the new names in the VCC and GND boxes under Signal names. Entering non-default signal names changes the settings in the Tool name list to Custom.

  6. If you want to use a non-default Library Mapping File (.lmf), under Library Mapping File, type the file name in the File name box, or browse to that location. A non-default Library Mapping Files must use proper Library Mapping Files format and syntax.

  7. To display messages about Library Mapping Files mapping during compilation, turn on Show information messages describing LMF mapping during compilation.

  8. If you want to restore settings to the original defaults for your design entry or synthesis tool, click Reset.

  9. Click OK.

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