Board-Level Page (Settings Dialog Box)

You open this dialog box by clicking EDA Tool Settings in the Settings dialog box, and then clicking Board Level.

Allows you to specify an EDA board-level symbol generation, signal integrity, or timing analysis tool and specify the output directory.

Board-level symbol:

Allows you to select FPGA Xchange to generate an FPGA Xchange-Format File (.fx, or select ViewDraw to generate PartMiner edaXML-Format File (.xml) for symbol generation and board-level verification with other EDA tools.

Scripting Information

Keyword: eda_board_design_symbol_tool

Settings: "FPGA Xchange (Symbol)" | "Viewdraw (Symbol)" | "<None>"

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Board-level signal integrity analysis:

Allows you to select HSPICE to generate HSPICE Simulation Deck Files (.sp) or IBIS to generate an IBIS Output File (.ibs).

Note: Turn on Enable model selector to use HSPICE or IBISmodels.

HSPICE model generation is available for supported device (Cyclone III, HardCopy, Stratix II, and Stratix II GX) families. For all other families, refer to the HSPICE models section of the Signal Integrity section on the Altera website.

IBIS model generation is fully supported for all devices supported by the Quartus II software, except HardCopy series, MAX II and Stratix II device families. For additional IBIS model device support and support files, refer to the IBIS models section of the Signal Integrity section on the Altera website.

Scripting Information

Keyword: eda_board_design_signal_integrity_tool

Settings: "IBIS (Signal Integrity)" | "HSPICE (Signal Integrity)" | "<None>"

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Board-level timing analysis:

Board-Level Timing Analysis—Allows you to select STAMP to create a Stamp model file for use with the Mentor Graphics Tau timing analysis tools.

Scripting Information

Keyword: eda_board_design_timing_tool

Settings: "Stamp (Timing)" | "<None>"

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Board-level boundary scan:

If your design targets a Stratix IV device, you can generate a Boundary Scan Description Language File (.bsd) when you run the EDA Netlist Writer. The resulting output file is named for the device package your design targets.

Scripting Information

Keyword: eda_board_design_boundary_scan_tool

Settings: "BSDL(Boundary Scan)" | "<None>"

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Specifying the Output Directory for Board-Level Tools:

Each output file type allows you to change the location you want to use as the output directory for the selected EDA tool. You can type or browse to a folder of your choice once you have selected a particular file type you would like to generate. The default name contains the type of tool or output format, followed by the tool name. For example, the default value for the ModelSim simulation software is simulation/modelsim, the default value for the board-level signal integrity analysis output format IBIS is board/ibis.

Scripting Information

Keyword: eda_netlist_writer_output_dir

Settings: <directory path>

If you select IBIS as your output format, you can turn on Enable model selector to generate all possible models for each I/O cell in the IBIS file. The default setting lists one model per I/O cell.

Scripting Information

Keyword: eda_ibis_model_selector

Settings: on | off

*default