Timing Analysis Page (Settings Dialog Box)

You open this dialog box by clicking EDA Tool Settings in the Settings dialog box, and then clicking Timing Analysis.

Allows you to specify options for generating VHDL Output File (.vho), Verilog Output File (.vo) and corresponding Standard Delay Format Output Files (.sdo) for use with other EDA timing analysis tools.

Tool name:

Specifies the EDA tool used for timing analysis

Scripting Information

Keyword: eda_timing_analysis_tool

Settings: "PrimeTime (Verilog)" | "PrimeTime (VHDL)" | "<None>"

*default

Run this tool automatically after compilation:

Directs the selected timing analysis EDA tool to start automatically after the Quartus II software compiles the design. The timing analysis tool processes the VHDL Output File (.vho), Verilog Output File (.vo), and Standard Delay Format Output Files (.sdo) generated during compilation.

Scripting Information

Keyword: eda_run_tool_automatically

Settings: on | off

*default

Format for output netlist:

Select VHDL to make the EDA Netlist Writer generates VHDL Output Files or Verilog to generate Verilog Output Files as the format for the netlist output of the active simulation or timing tool.

Output directory:

Type or browse to the location you want to use as the output directory for the specified EDA simulation tool. The default name contains the type of tool or output format, followed by the tool name. For example, the default value for the ModelSim simulation software is simulation/modelsim.

Scripting Information

Keyword: eda_netlist_writer_output_dir

Settings: <output directory>

*default

Time scale:

Directs the EDA Netlist Writer to represent timing delays with the specified time units in Verilog Output Files or Standard Delay Format Output Files. The selected value for the Time Scale option can be between 1 picosecond and 1 millisecond.

Scripting Information

Keyword: eda_time_scale

Settings: <time>

default = 1ps

Map illegal HDL characters:

Turning this option on directs the EDA Netlist Writer to map illegal characters for VHDL or Verilog HDL.

If you selected VHDL in the Format for output netlist list, the EDA Netlist writer maps non-alphanumeric characters, including brackets ([]), parentheses, (()), angle brackets (<>), and braces ({}) to (_a) in . This option generates VHDL 1987 compatible names.

If you selected Verilog in the Format for output netlist list, the EDA Netlist writer maps the vertical bar (|), tilde (~), and colon (:) characters in Quartus II hierarchical node names to the legal Verilog HDL characters z, x, and underscore (_), respectively, in Verilog Output File. Turning on this option also maps other illegal non-alphanumeric characters, including brackets ([]), parentheses, (()), angle brackets (<>), and braces ({}) to underscore (_).

Scripting Information

Keyword: eda_map_illegal_characters

Settings: on | off

*default

Truncate long hierarchy paths:

Directs the EDA Netlist Writer to truncate hierarchical node names to 80 name characters.

Scripting Information

Keyword: eda_truncate_long_hierarchy_paths

Settings: on | off

*default

Flatten buses into individual nodes:

Directs the EDA Netlist Writer to flatten all buses when creating VHDL Output Files. You should turn on this option if your EDA tool does not support buses.

Scripting Information

Keyword: eda_flatten_buses

Settings: on | off

*default

More Settings:

Opens the More Timing Analysis Settings dialog box, which allows you to enable additional options for use with third-party timing analysis tools.