A Verilog Hardware Description Language (HDL) standard netlist file (with the extension .vo) that is generated by the Quartus II Compiler.
The Verilog Output File can be imported into an industry-standard Verilog HDL simulation or timing analysis tool. The Verilog Output File cannot be compiled with the Quartus II Compiler.
You can specify that the Compiler generates a Verilog Output File after a successful compilation by selecting the name of a specific Verilog HDL simulation or timing analysis tool, or by selecting Custom Verilog HDL from the Tool name list and specifying options in the Simulation or Timing Analysis pages of the Settings dialog box.
You can also generate a Verilog Output File by using the Start EDA Netlist Writer command. You can use this command if you have already compiled the design and want to change the EDA tool settings and generate a Verilog Output File for another EDA tool.
The Compiler places the generated Verilog Output File into a tool-specific directory within the current project directory. For EDA simulation tools, the Verilog Output File is placed in the /<project directory>/simulation/<EDA simulation tool> directory. For EDA timing analysis tools, the Verilog Output File is placed in the /<project directory>/timing/<EDA timing analysis tool> directory. If you select Custom Verilog HDL for simulation or timing analysis, the Verilog Output File is placed in the /<project directory>/simulation/custom or the /<project directory>/timing/custom directory, respectively.
The file name of the Verilog Output File is the top-level design entity name with a .vo extension. The file name of the Standard Delay Format Output File (.sdo) is the top-level design entity name with a "_v" appended to the project name and an .sdo extension (for example, <top-level design name>_v.sdo).
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