Setting Up a Project with the ModelSim Software

You can run the Mentor Graphics ModelSim PE or SE software from the ModelSim interface or with command-line commands.

If you have not already done so set up the ModelSim working environment.
If you are performing a timing simulation, to generate the Verilog Output File (.vo) or VHDL Output File (.vho):
1. Specify EDA tool settings in the Quartus II software.
2. Compile the design with the Quartus II software.

Note: If you have already compiled the design, and want to specify different EDA tools settings and generate a Verilog Output File (.vo), VHDL Output File (.vho), and Standard Delay Format Output File (.sdo) without recompiling the design, you can use the Start EDA Netlist Writer command.

You can also use the Start EDA Netlist Writer command to generate the following types of files:

Script files to generate Value Change Dump File (.vcd) in EDA simulation tools

Start the ModelSim software.

To specify the project directory:

On the File menu, click Change Directory.
In the Choose a Directory dialog box, type the path to the project directory in the Directory Name box.

or

In the Look in list, select the project directory.
Click Open.

Note: If you are performing a functional simulation, the project is the directory that contains your design files. If you are performing a timing simulation, the project directory is the <project directory>\simulation\modelsim directory or the location you specified in the Output directory box of the Simulation in the Settings dialog box.

To create a new work library:

On the File menu, point to New, and then click Library. The Create a New Library dialog box appears.
Under Create, select a new library and a logical mapping to it.
In the Library Name box, type the library name.
In the Library Maps to list select the work library.

Note: When you run the ModelSim software independently from the Quartus II software, you should name your library work. When you run the ModelSim software automatically from the Quartus II software, your library is named ModelSim_work automatically and located in the current Quartus II project directory.

If you have not already done so, perform Setting Up the ModelSim Working Environment.
If you are performing a timing simulation, to generate the Verilog Output File (.vo) or VHDL Output File (.vho):
1. Specify EDA tool settings in the Quartus II software.
2. Compile the design with the Quartus II software.

You can also use the Start EDA Netlist Writer command to generate the following types of files:

Script files to generate Value Change Dump File (.vcd) in EDA simulation tools

Start the ModelSim software.
Change to the directory where the ModelSim libraries are located after they are compiled.
To create a new work library, type the following command at the ModelSim prompt:

vlib work

ModelSim compiles the design files to library work by default.
To change the default library type the following commands at the ModelSim prompt:

vlib <user defined library>

vmap work<user defined library>

Note: When you run the ModelSim software automatically from the Quartus II software, your work library is automatically mapped to rtl_work for RTL simulation and gate_work for gate level simulation. The libraries are created in the <project directory>\simulation\modelsim directory or the location you specified in the Output directory box of the Simulation page in the Settings dialog box.