Note: The EDA Netlist Writer generates the VHDL Output File and the SDF Output File and places them in the specified output directory. The default location is /<project directory>/simulation/vcsmx.
If you have compiled the design, and want to specify different EDA tools settings and generate a Verilog Output File (.vo), VHDL Output File (.vho), and Standard Delay Format Output File (.sdo) without recompiling the design, you can use the Start EDA Netlist Writer command. You can also use the Start EDA Netlist Writer command to generate script files to generate Value Change Dump File (.vcd) in EDA simulation tools.
Add the following lines to your .synopsys_vss.setup file to include the mapping information for the work library, and to direct the VCS MX software to use the timing simulation libraries during simulation:
WORK ><work library>
lpm ><work library>
altera_mf ><work library>
<device family>><work library>
<work library>>:<physical path to work library>
If your design targets the Stratix GX family add:
stratixgx_gxb ><work library>
altgxb ><work library>
If your design targets the Stratix II GX family add:
alt2gxb ><work library>
stratixiigx_hssi ><work library>
Create a work library in the project directory by typing the following command at a command prompt:
mkdir<work library>
Note: Altera recommends using the Synopsys VCS MX default library names when you create a library. You should name the VCS MX software libraries as follows:
When you run the VCS MX software independently from the Quartus II software, you should name your library work.
When you run the VCS MX software automatically from the Quartus II software, your library is automatically named scsim_work under the current project directory, and the work alias is mapped to the scsim_work directory.
To compile the VHDL Output File, test bench file (if you are using one), and Altera post-fitting libraries:
If your design contains the altgxb or alt2gxb megafunctions, compile the altgxb or alt2gxb libraries by typing the following commands at a command prompt:
Important: If your design contains the altgxb megafunction or the alt2gxb megafunction, please refer to the appropriate megafunction topic for required settings information.
For each of the appropriate timing simulation libraries, type the following commands at a command prompt:
If your design targets Stratix III or Cyclone III family, you must also compile the following files by typing the following commands at a command prompt:
To start a simulation session by elaborating and compiling, and to create the scsim executable to simulate the design, type the following command at the command prompt:
scs<top-level entity>
To simulate the design, type the following command at a command prompt (where <region> is the hierarchical instance name of the design in the test bench file, using "/" as hierarchy separator:
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