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Home > Support > Design Software > Synthesis Tools > Design Compiler > Creating a Design For Use with the Design Compiler Software Print This Page Subscribe to Email Creating a Design For Use with the Design Compiler Software You can create Verilog HDL design files with the Quartus II Text Editor or another standard text editor for use with the Synopsys Design Compiler software. To create a Verilog or VHDL design for use with the Design Compiler software, follow these steps: If you have not already done so, set up the Design Compiler working environment. Instantiate logic functions with a Component Instantiation, and include a Module Declaration (Verilog) or Component Declaration (VHDL) for each function. Altera provides simulation models for the following types of logic functions: Primitives in the Design Compiler Technology Libraries, other Altera macrofunctions, or non-parameterized megafunctions for which no simulation models or technology library support is available. These functions are treated as "black boxes" during processing with the Design Compiler. The following examples show how to instantiate these primitives, macrofunctions, or megafunctions: Primitive and Old-Style Macrofunction Instantiation Example for VHDL Primitive and Old-Style Macrofunction Instantiation Example for Verilog HDL   Important: If you instantiate a black box logic function for which no simulation/technology library support is available, create a hollow-body design description in order to prevent the Design Compiler from issuing a warning message. If you instantiate a black box logic function, you must create a Library Mapping File (.lmf) to map the function to an equivalent Quartus II function before you compile the project with the Quartus II software. Architecture Control Logic functions in the alt_mf library, which includes the a_8count, a_8mcomp, a_8fadd, and a_81mux functions. The following examples show how to instantiate these primitives: Architecture Control Logic Function Instantiation Example for VHDL Architecture Control Logic Function Instantiation Example for Verilog HDL For VHDL designs, use the DesignWare up/down counter function (DW03_updn_ctr). Creating a Design For Use with the Design Compiler Software MegaCore functions are offered by Altera and by members of the Altera Megafunction Partners Program (AMPP). The OpenCore feature in the Quartus II software allows you to instantiate, compile, and simulate MegaCore functions before deciding whether to purchase a license for full device programming and post-compilation simulation support. To continue with the Design Compiler design flow, synthesize and optimizing a design with the Design Compiler software.     Rate This Page

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