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Home > Support > Design Software > Synthesis Tools > Design Compiler > Setting Up the DesignWare Interface (Design Compiler Software) Print This Page Subscribe to Email Setting Up the DesignWare Interface (Design Compiler Software) The DesignWare interface synthesizes designs by operator inference for all Altera devices supported by the Quartus II software except MAX 3000 and MAX 7000 devices. It replaces the HDL operators +, -, >, <, >=, and <= with optimized design implementations. Altera provides DesignWare synthetic libraries that precompiled for the current version of Synopsys tools. These library files are located in the /usr/quartus/eda/synopsys/dc/syn/<device family>/lib directory.   Note: The information presented here assumes that you are using C shell and that your Quartus II system directory is /usr/quartus. If not, you must use the appropriate syntax and procedures to set environment variables for your shell.   To set up the DesignWare interface: If you have not already done so, set up the Design Compiler working environment. Add synthetic_library and define_design_lib parameters to your .synopsys_dc.setup configuration file as shown in the following table. Device Family Parameters to Add to the .synopsys_dc.setup File ACEX 1K synthetic_library = {acex1k.sldb};  link_library = {acex1k.sldb acex1k.db};  define_design_lib DW_ACEX1K -path /usr/quartus/eda/synopsys/dw/lib  APEX 20K synthetic_library = {apex20k-3.sldb};  link_library = {apex20k-3.sldb apex20k-3.db};  define_design_lib DW_APEX20K-3 -path /usr/quartus/eda/synopsys/dw/lib  APEX 20KC synthetic_library = {apex20kc-3.sldb};  link_library = {apex20kc-3.sldb apex20kc-3.db};  define_design_lib DW_APEX20KC-3 -path /usr/quartus/eda/synopsys/dw/lib  APEX 20KE synthetic_library = {apex20ke-3.sldb};  link_library = {apex20ke-3.sldb apex20ke-3.db};  define_design_lib DW_APEX20KE-3 -path /usr/quartus/eda/synopsys/dw/lib  APEX II synthetic_library = {apexii-3.sldb};  link_library = {apexii-3.sldb apexii-3.db};  define_design_lib DW_APEXII-3 -path /usr/quartus/eda/synopsys/dw/lib  Arria GX synthetic_library = {arriagx.sldb};  link_library = {arriagx.sldb arriagx.db};  define_design_lib DW_ARRIAGX -path /usr/quartus/eda/synopsys/dw/lib  Cyclone synthetic_library = {cyclone.sldb};  link_library = {cyclone.sldb cyclone.db};  define_design_lib DW_CYCLONE -path /usr/quartus/eda/synopsys/dw/lib  Cyclone II synthetic_library = {cycloneii.sldb};  link_library = {cycloneii.sldb cycloneii.db};  define_design_lib DW_CYCLONEII -path /usr/quartus/eda/synopsys/dw/lib  Cyclone III synthetic_library = {cycloneiii.sldb};  link_library = {cycloneiii.sldb cycloneiii.db};  define_design_lib DW_CYCLONEIII -path /usr/quartus/eda/synopsys/dw/lib  FLEX 6000 synthetic_library = {flex6000-(2|3).sldb};  link_library = {flex6000-(2|3).sldb flex6000-(2|3).db};  define_design_lib DW_FLEX6000-(2|3) -path /usr/quartus/eda/synopsys/dw/lib  FLEX 10K synthetic_library = {flex10ke-3.sldb};  link_library = {flex10ke-3.sldb flex10ke-3.db};  define_design_lib DW_FLEX10KE-3 -path /usr/quartus/eda/synopsys/dw/lib  HardCopy II synthetic_library = {hardcopyii.sldb};  link_library = {hardcopyii.sldb hardcopyii.db};  define_design_lib DW_HARDCOPYII -path /usr/quartus/eda/synopsys/dw/lib  MAX II synthetic_library = {maxii.sldb};  link_library = {maxii.sldb maxii.db};  define_design_lib DW_MAXII -path /usr/quartus/eda/synopsys/dw/lib  Stratix synthetic_library = {stratix-5.sldb};  link_library = {stratix-5.sldb stratix-5.db};  define_design_lib DW_STRATIX-5 -path /usr/quartus/eda/synopsys/dw/lib  Stratix GX synthetic_library = {stratixgx.sldb};  link_library = {stratixgx.sldb stratixgx.db};  define_design_lib DW_STRATIXGX -path /usr/quartus/eda/synopsys/dw/lib  Stratix II synthetic_library = {stratixii.sldb};  link_library = {stratixii.sldb stratixii.db};  define_design_lib DW_STRATIXII -path /usr/quartus/eda/synopsys/dw/lib  Stratix II GX synthetic_library = {stratixiigx.sldb};  link_library = {stratixiigx.sldb stratixiigx.db};  define_design_lib DW_STRATIXIIGX -path /usr/quartus/eda/synopsys/dw/lib  Stratix III synthetic_library = {stratixiii.sldb};  link_library = {stratixiii.sldb stratixiii.db};  define_design_lib DW_STRATIXIII -path /usr/quartus/eda/synopsys/dw/lib  Specify the libraries listed in the following table as the synthetic library for the synthetic_library parameter and as the first of your link libraries for the link_library parameter in the .synopsys_dc_setup file. DesignWare Synthetic Libraries Altera Device Family Synopsys Design Compiler ACEX 1K synthetic library acex1k.sldb APEX 20K synthetic library apex20k-3.sldb APEX 20KC synthetic library apex20kc-3.sldb APEX 20KE synthetic library apex20ke-3.sldb APEX II synthetic library apexii-3.sldb Arria GX synthetic library arriagx.slb Cyclone synthetic library cyclone.sldb Cyclone II synthetic library cycloneii.sldb Cyclone III synthetic library cycloneiii.sldb FLEX 6000 synthetic library flex6000-2.sldb flex6000-3.sldb FLEX 10K synthetic library flex10ke-3.sldb HardCopy II synthetic library hardcopyii.sldb Max II synthetic library maxii.sldb Stratix synthetic library stratix-5.sldb Stratix GX synthetic library stratixgx.sldb Stratix II synthetic library stratixii.sldb Stratix II GX synthetic library stratixiigx.sldb Stratix III synthetic library stratixiii.sldb If necessary, compile the DesignWare libraries. Altera provides precompiled DesignWare libraries, as described above. However, Altera also provides compilable source files and scripts that allow you to automate the compilation process. These source files allow you to use DesignWare with any version of the Design Compiler. They also allow you to install components whose source is written in VHDL. To compile the DesignWare libraries for all Altera device families listed in Table 2, type the following commands at the UNIX prompt: cd /usr/quartus/eda/synopsys/bin  dw_flex.sh  To continue with the Design Compiler design flow, proceed to Creating a Design for Use with the Design Compiler Software.     Rate This Page

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