Synthesizing and Optimizing a Design with the Design Compiler Software

The Quartus II software can process a VHDL or Verilog HDL file that the Synopsys Design Compiler software synthesized, saved as an EDIF 2 0 0 netlist file, and imported into the Quartus II software.

To synthesize and optimize a VHDL or Verilog HDL design with the Design Compiler software for use with the Quartus II software:

If you have not already done so, create a design for use with the Design Compiler software.

To start the Design Compiler software in the graphical user interface, type the following commands at the command prompt:

dc_shell design_analyzer

Analyze and then compile the design with the Design Compiler or Design Analyzer software. The VHDL Compiler or HDL Compiler for Verilog software automatically translates the design into Synopsys database (.db) format. For some types of projects, you must follow these steps before you process the design:

If you are compiling an ACEX 1K, APEX 20K, APEX 20KC, APEX 20KE, APEX II, Cyclone, Cyclone II, Cyclone III, FLEX 10K, MAX II, Stratix, Stratix II, Stratix II GX, Stratix III, or Stratix GX design, that includes RAM or ROM functions:
1. (VHDL designs only) Because the VHDL Compiler software does not support the data type string for the Generic Clause, enter the following command at the dc_shell prompt before you read the design:

hdlin_translate_off_skip_text=true

1. The timing model (.lib) generated by the genmem utility contains pin-to-pin delay information the Design Compiler software can use. Add this timing model to the existing library so that the compiler can access the timing information. Refer to the following table and at the dc_shell prompt, type one of the commands :

Device Family	Commands for Adding Timing Models to the Existing Libraries
ACEX 1K	`read -f db acex1k.dbupdate_lib acex1k`<RAM/ROM function name>`.lib`
APEX 20K	`read -f db apex20k-3.dbupdate_lib apex20k-3`<RAM/ROM function name>`.lib`
APEX 20KC	`read -f db apex20kc-3.dbupdate_lib apex20kc-3`<RAM/ROM function name>`.lib`
APEX 20KE	`read -f db apex20ke-3.dbupdate_lib apex20ke-3`<RAM/ROM function name>`.lib`
APEX II	`read -f db apexii-3.dbupdate_lib apexii-3`<RAM/ROM function name>`.lib`
Cyclone	`read -f dbcyclone.dbupdate_lib cyclone`<RAM/ROM function name>`.lib`
Cyclone II	`read -f dbcyclone.dbupdate_lib cyclone`<RAM/ROM function name>`.lib`
Cyclone III	read -f dbcyclone.db`update_lib cyclone`<RAM/ROM function name>`.lib`
FLEX 10K and ACEX 1K	`read -f db flex10ke-3.dbupdate_lib flex10ke-3`<RAM/ROM function name>`.lib`
MAX II	`read -f db maxii-3.dbupdate_lib maxii-3`<RAM/ROM function name>`.lib`
Stratix	`read -f db stratix-3.dbupdate_lib stratix-3`<RAM/ROM function name>`.lib`
Stratix GX	`read -f dbstratixgx.dbupdate_libstratixgx`<RAM/ROM function name>`.lib`
Stratix II	`read -f dbstratixii.dbupdate_libstratixii`<RAM/ROM function name>`.lib`
Stratix II GX	`read -f db stratixiigx.dbupdate_lib stratixiigx`<RAM/ROM function name>`.lib`
Stratix III	`read -f db stratixiii.dbupdate_libstratixiii` <RAM/ROM function name>`.lib`

1. (Optional) To update the flex10k[<speed grade>].db file with the RAM/ROM timing information, refer to the following table and type one of the commands at the dc_shell prompt:

Device Family	Commands for Updating the flex10k[<speed grade>].db file with the RAM/ROM Timing Information
ACEX 1K	`write_lib acex1k -o acex1k.db`
APEX 20K	`write_lib apex20k-3 -o apex20k-3.db`
APEX 20KC	`write_lib apex20kc-3 -o apex20kc-3.db`
APEX 20KE	`write_lib apex20ke-3 -o apex20ke-3.db`
APEX II	`write_lib apexii-3 -o apexii-3.db`
Cyclone	`write_lib cyclone -o cyclone.db`
Cyclone II	`write_lib cycloneii -o cycloneii.db`
Cyclone III	write_lib cycloneiii -o cycloneiii.db
FLEX 10K and ACEX 1K	`write_lib flex10ke-3 -o flex10ke-3.db`
MAX II	`write_lib maxii-3 -o maxii-3.db`
Stratix	`write_lib stratix-3 -o stratix-3.db`
Stratix GX	`write_lib stratixgx -o stratixgx.db`
Stratix II	`write_lib stratixii -o stratixii.db`
Stratix II GX	`write_lib stratixiigx -o stratixiigx.db`
Stratix III	`write_lib stratixiii -o stratixiii.db`

(Optional) Enter resource assignments. The Quartus II software allows you to make a variety of resource and device assignments for projects. Resource assignments are used to assign logic functions to a particular pin, logic cell, I/O cell, embedded cell, row, column, Logic Array Block (LAB), Embedded System Block (ESB), Embedded Array Block (EAB), MegaLAB structure, row, column, fast region, custom region, section, chip, clique, local routing, logic option, or timing assignments or requirements. In the Quartus II software, you can enter all types of resource and device assignments with the Assignment Editor. You can also enter assignments in the Quartus II Timing Closure Floorplan.

For additional information on how the Design Compiler synthesizes and optimizes a design, refer to the Synopsys Design Compiler Reference Manual or Design Analyzer Reference Manual.

(Optional) View the optimized design with the Design Analyzer. The Design Analyzer uses the altera.sdb library to display optimized designs generated by the Design Compiler.

(Optional) To view Synopsys-generated timing information and generate a file detailing primitive usage, type the following commands at the dc_shell prompt:

report_timing report_reference > <file name>

Specify EDA tool settings and compile the design in the Quartus II software.