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Home > Support > Design Software > Synthesis Tools > DC FPGA > Creating a Design for Use with the DC FPGA Software Print This Page Subscribe to Email Creating a Design for Use with the DC FPGA Software Projects in the Synopsys Design Compiler FPGA software can contain of EDIF netlist files, VHDL Design Files (.vhd), or Verilog Design Files (.v) or files created in the Synopsys internal database format (with the .db extension). To create a Verilog HDL or VHDL design file for use with the DC FPGA software: If you have not already done so, set up the DC FPGA working environment. Enter a VHDL or Verilog HDL design in the Quartus II Text Editor or another standard text editor and save it in the project directory. To use Altera-provided megafunctions in a design, use the MegaWizard Plug-In Manager to generate a custom megafunction variation. Refer to Creating and Instantiating Altera-Provided Functions in Other EDA Tools for examples on how to use Altera-provided megafunctions and library of parameterized modules (LPM) functions in other EDA design entry/synthesis tools. Once you create a megafunction variation, you can instantiate it as a black box entity in the design. In addition, the DC FPGA software automatically recognizes certain types of HDL code and maps it to Altera megafunctions during synthesis. You can describe the design in Verilog HDL or VHDL and use the DC FPGA software to infer arithmetic and relational operators, counters, RAM, ROM, and DSP functions directly from HDL code. If you are performing formal verification with the Formality software, you must instantiate RAM as a black box entity. To continue with the DC FPGA design flow, assign design constraints with the DC FPGA software.     Rate This Page

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