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Home > Support > Design Software > Synthesis Tools > DC FPGA > Generating EDIF Netlist Files with the DC FPGA Software Print This Page Subscribe to Email Generating EDIF Netlist Files with the DC FPGA Software You can perform synthesis, view report information, and generate EDIF netlist files for a project in the Synopsys Design Compiler FPGA software. The DC FPGA software generates a Tcl Script File (.tcl) that you can use to set up your project and compile your design in the Quartus II software. To synthesize the design and generate the Tcl Script File with the DC FPGA software: If you have not already done so, assign design constraints with the DC FPGA software. To synthesize the design, type the following command at the DC FPGA shell prompt: compile  The DC FPGA software provides different commands for viewing the results of synthesis. To generate timing and resource usage information for your design, type the following commands at the DC FPGA shell prompt: report_timing  report_fpga    Note: You can also generate log files using these commands. For more information on generating report information using the DC FPGA software, refer to the Synopsys DC FPGA User Guide.   Once you have synthesized and optimized your design, to create an EDIF Input File (.edf) for all levels of hierarchy in your design, type the following command at the DC FPGA shell prompt: write -format edif -hierarchy -output <EDIF output file name>.edf  To generate the Tcl Script File for creating a project and compiling the design in the Quartus II software, type the following command at the DC FPGA shell prompt: write_par_constraint <Tcl Script File name>.tcl    Note: The Quartus II software currently supports only EDIF Input Files generated by the DC FPGA software.   Create and compile the project in the Quartus II software by typing one of the following commands: quartus_sh -t <Tcl Script File name>.tcl  (from the command prompt) or source <Tcl Script File name>.tcl  (from the Quartus II Tcl Console)   Note: If you do not want the Quartus II software to immediately compile the design after creating the project, remove the following lines from the Tcl Script File: load_package flow execute_flow -compile You can also use the New Project Wizard on the File menu to manually create the project in the Quartus II software, using the EDIF Input File generated by the DC FPGA software.   You can also use a Tcl Script File to perform all the tasks in this topic and in the Assigning Design Constraints with the DC FPGA Software topic. You can create the Tcl Script File and run it in the DC FPGA software by typing one of the following commands: fpga_shell-t -f <path to Tcl Script File>/<Tcl Script File name>.tcl  (from the command prompt) or source <path to Tcl Script File>/<Tcl Script File name>.tcl  (from the DC FPGA shell prompt)     Rate This Page

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