To use the Quartus II software with Synopsys Design Compiler FPGA software, you must install the Quartus II software, then establish an environment that facilitates entering and processing designs.
To set up the DC FPGA working environment:
Make sure you have installed the following versions of the Quartus II software and the DC FPGA software:
Synopsys
Altera
DC FPGA
version 2005.09
Quartus II version 7.2
The DC FPGA software supports the Cyclone, Stratix, and Stratix GX device families.
Note: The Quartus II Software Release Notes are available on the Altera website and provide up-to-date information on which versions of Synopsys applications the current version of the Quartus II software supports. The Quartus II readme.txt file provides information on installation and operating requirements. You should read the Release Notes and readme.txt file before installing the Quartus II software. After installation, you can open the Release Notes and readme.txt file from the Quartus II Help menu.
Go to Quartus II Installation in the Quartus II Installation & Licensing for UNIX and Linux Workstation manual for more information on installation and details on the directories that are created during Quartus II installation.
To map to Altera device libraries, set the search path, and make other project settings for the DC FPGA software, add the following lines to the .synopsys_dc.setup file for your project (where <version> is the current version of the DC FPGA software and <device family> is the current target device family for your design):
set search_path ". $dcfpga_lib_path/<device family>$search_path"
set target_library "<device family>.db"
set synthetic_library "tmg.sldb altera_mf.sldb lpm.sldb"
set link_library "*<device family>.db tmg.sldb altera_mf.sldb lpm.sldb"
define_design_lib altera_mf -path $dcfpga_lib_path/<device family>/altera_mf
define_design_lib LPM -path $dcfpga_lib_path/<device family>/LPM
set cache_dir_chmod_octal "1777"
set edifout_netlist_only "true"
set edifout_power_and_ground_representation "net"
set edifout_ground_net_name "GND"
set edifout_power_net_name "VDD"
set hdlin_enable_vpp "true"
set post_compile_cost_check "false"
set_fpga_defaults altera_<device family>
Altera provides the following synthetic libraries for synthesizing designs in the Synopsys DC FPGA software. The libraries are located in the /<DC FPGA installation directory>/dc_fpga/<version>/libraries/<version> directory (where <version> is the current version of the DC FPGA software you are using.
Library Name
Description
cyclone.db
Technology library for Cyclone designs.
stratix.db
Technology library for Stratix designs.
stratixgx.db
Technology library for Stratix GX designs.
lpm.sldb
Synthetic library for library of parameterized modules (LPM) version 2 2 0.
altera_mf.sldb
Synthetic library for Altera-specific megafunctions.
Literature
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