To generate Quartus II–compatible EDIF netlist files, select the optimized design implementation and click the Export Netlist button on the toolbar.
In the Export Netlist dialog box, specify the following options:
In the Export Directory box, specify the name and location of the directory for the EDIF netlist files.
Under Place and Route, select the EDIF netlist file's output bus in the Bus Style list. The Quartus II software accepts either flattened or unflattened buses. In the FPGA Compiler II software, the default setting, EXPAND, flattens each bus by writing each bus bit as an individual I/O port. To export an EDIF netlist file without flattening the bus names, select any of the other settings, which include delimiters for different bus notations:[], <>, (), and {}.
Note: If you are using a custom megafunction variation for content-addressable memory (CAM), ClockLock PLL, LVDS, or RAM functions generated by the MegaWizard Plug-In Manager, you must select %s{%d:%d} in the Bus Style list.
To generate a VHDL or Verilog HDL netlist file for functional simulation prior to Quartus II compilation, select a language option (VHDL or Verilog) from the Output Format list. Otherwise, NONE is selected by default.
To close the Export Netlist dialog box, click OK. The FPGA Compiler II software creates the following Quartus II–compatible files:
<design name>.edf (EDIF format)
<design name>.tcl, a Tcl Script File (.tcl) that contains a Tcl script for compiling the design with the Quartus II software
<design name>.lmf, a Library Mapping File (.lmf) that maps FPGA Compiler II functions to Quartus II functions
Copy all the output files to a Quartus II project directory. Compile the design to process the <design name>.edf file with the Quartus II software.
Note: You must specify the FPGA Compiler II generated <design name>.lmf as the Library Mapping File for the project when specifying the EDA tool input settings.
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