Creating and Instantiating a Verilog HDL Function for Use with the FPGA Compiler II Software
You can create or modify design files that contain custom megafunction variations of Altera-provided functions. You can then instantiate the custom megafunction variations in a design file for use with the Synopsys FPGA Compiler II and Quartus II software. This procedure shows only how to instantiate an LVDS function using Verilog HDL; however, you can use similar procedures to instantiate other Altera-provided functions.
Open the MegaWizard Plug-In Manager and specify appropriate options for the megafunction you want to instantiate.
The MegaWizard Plug-In Manager generates custom megafunction variations that are based on Altera-provided megafunctions, including library of parameterized modules (LPM) functions, as well as Altera megafunctions.
Refer to the following example to create a Verilog HDL custom megafunction variation of the altlvds_rx function:
To prepare the Verilog HDL design for synthesis with the FPGA Compiler II software, you must specify that the tool should treat the design file created in the MegaWizard Plug-In Manager as a "black box." The software then makes the correct connections to the ports in the EDIF netlist file (.edf). The Quartus II software reads in the EDIF netlist file as an EDIF Input File (.edf) and processes the instantiated megafunction. To treat the design file for the megafunction as a "black box," refer to the following example:
Note: The design file generated by the MegaWizard Plug-In Manager must be in the same directory as the EDIF Input File or added to the Quartus II project.
If necessary, perform a functional simulation with the VCS software or another simulation tool. Refer to the following example for a sample script that you can use to perform a functional simulation:
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