Analyzing Design Results with the Synplify Software
You can use the optional Synplify HDL Analyst to graphically analyze and evaluate the performance of a design. The Synplify HDL Analyst generates Register Transfer Level (RTL) schematics, as well as technology-mapped, gate-level schematics. You can instantly identify and fix potential problems earlier in the design cycle by cross-probing between the RTL schematics, gate-level schematics, and HDL source code. The Synplify HDL Analyst also highlights critical paths within the design to show which signals require optimization for performance. After you determine the critical speed paths, you can add timing constraints either to the VHDL or Verilog HDL source file or to a separate Synplify Design Constraints File (.sdc) to improve design performance. You can also use the Synplify HDL Analyst to cross-probe nodes in the Synplify HDL Analyst with the corresponding nodes in the Quartus II Timing Closure Floorplan.
To use the Synplify HDL Analyst after synthesizing your design with Synplify software, go through the following steps:
On the HDL_Analyst menu, click RTL View to view the RTL schematic. When you select this view, the HDL Analyst displays a graphical representation of the design and the mouse pointer becomes a plus (+) symbol.
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On the HDL_Analyst menu, click Technology View to view the gate-level schematic. When you select this view, the HDL Analyst displays a graphical representation of the design and the mouse pointer becomes a plus (+) symbol.
In either the RTL or Technology View, perform one or more of the following actions:
Click the plus (+) symbol pointer on a port name or symbol to highlight the node in the Quartus II Timing Closure Floorplan.
Double-click the plus (+) symbol pointer on a port name or symbol to cross-probe your VHDL or Verilog HDL source design files in the Synplify software.
Note: Because the Synplify software combines the a + b and a - b operations, cross-probing highlights the Case Statement that defines both functions.
To select specific signals quickly in your design, on the HDL_Analyst menu, click Find.
To highlight the critical paths in the design, on the HDL_Analyst menu, click Show Critical Path.
To show only the nodes you have selected, on the HDL_Analyst menu, click Filter Schematic.
You can also highlight nodes in the Quartus II Timing Closure Floorplan to cross-probe the corresponding nodes in the Synplify HDL Analyst.
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