Select the TimeQuest Timing Analyzer for designs targeting supported device(Arria GX, Cyclone II, Cyclone III, HardCopy, Stratix, Stratix II, Stratix II GX, and Stratix III) families, or the Classic Timing Analyzer.
Note: the Classic Timing Analyzer supports the PrimeTime software for designs targeting supported device(ACEX 1K, APEX 20K, APEX 20KC, APEX 20KE, APEX II, Cyclone, FLEX 6000, FLEX 10KE, MAX 3000, MAX 7000, and MAX II) families.
Compile the design with the Quartus II software.
Note: During compilation, the Quartus II software generates a <design name>_pt_v.tclTcl Script File (.tcl) for Classic Timing Analyzer flow, and <design name>.pt.tcl for TimeQuest Timing Analyzer flow. This file sets up the PrimeTime environment for performing a timing verification, and places it in the \<project directory>\timing\primetime\ directory. The TCL Script File contains:
On the Processing menu, point to Start, and then click Start Classic Timing Analyzer (Fast Timing Model) to perform a minimum timing analysis.
On the Processing menu, point to Start, and then click Start EDA Netlist Writer to generate the output netlist files.
Note: The EDA Netlist Writer generates a <design name>_fast.vo Verilog Output File and places it in the specified output directory. The default location is <project directory>\timing\primetime\.
To start the PrimeTime software in command-line mode, type pt_shell at the command prompt.
Source the Tcl Script File with the PrimeTime shell. Type source<design name>_pt_(v | vhd).tcl for a file generated with the Classic Timing Analyzer or source <design name>.pt.tcl for a file generated with the TimeQuest Timing Analyzer.
For Classic Timing Analyzer, set the mode of operation for the PrimeTime memory models for RAM ATOMs, use either the read_during_write mode or the no_read_during_write mode (the default is read_during_write) by typing one of the following commands at the PrimeTime shell prompt:
Literature
> 
at the command prompt.
