FPGA, CPLD, and ASIC solutions from Altera
  • Download Center
  • Literature
Sign in/register
myAltera Account
Welcome
  •   myAltera
  •   Logout
  • Products
    • Devices
    • Design Software
    • Intellectual Property
    • Development Kits/Cables
    • Design & Support Services
    • Literature
  • End Markets
    • Automotive
    • Broadcast
    • Computer & Storage
    • Consumer
    • Industrial
    • Medical
    • Military
    • Test & Measurement
    • Wireless
    • Wireline
  • Technology
    • DSP
    • External Memory
    • Embedded Processing
    • Transceivers
    • Parallel I/O
    • Signal Integrity
    • System Integration
  • Training
    • Training Courses
    • University Program
    • Webcasts & Videos
    • Demonstrations
    • Events Calendar
  • Support
    • Design & Support Resources
    • Knowledge Database
    • Devices
    • Design Software
    • Intellectual Property
    • Development Kits/Cables
    • Design Examples
    • Downloads
    • User Communities/Forums
    • mySupport
  • About Altera
    • About Us
    • Environmental
    • Customer Successes
    • Partners
    • Newsroom
    • Investor Relations
    • Jobs
    • Contact Us
  • Buy Online
    • Devices
    • Design Software
    • Development & Education Kits
    • Cables & Programming Hardware
    • Intellectual Property
  • Entire Site
  • Part Number
  • Knowledge Database
  • Support & Technical Docs
  • Forums & Wiki
Username:  
Password:  
 
Forgot my username or password
Don't have myAltera account? Register Now.
Enter your email address:

Synthesis and Netlist Viewers Resource Center

Home > Support > Design Software > Synthesis & Netlist Viewers

The Quartus® II software includes advanced integrated synthesis and interfaces with other third-party synthesis tools. The Quartus II software also offers schematic netlist viewers that you can use to analyze a design's structure and see how the software interpreted your design. For additional information on synthesis and netlist viewers, see:

  • Synthesis Documentation
  • Synthesis Training and Demonstrations
  • Netlist Viewers Documentation
  • Netlist Viewers Training and Demonstrations

For a brief overview of synthesis features, refer to the Synthesis product page.

To search for known issues and technical support solutions related to synthesis or the netlist viewers, use Altera’s Knowledge Database. You can also visit the Altera® Forum to connect and discuss technical issues with other Altera users.

For further technical support, use mySupport to create, view, and update service requests.

Synthesis Resources

Table 1 provides links to available documentation on Quartus II integrated synthesis and interfaces with third-party synthesis tools.

Table 1. Synthesis Documentation
Title Description
Quartus II Integrated Synthesis (PDF) This chapter of the Quartus II Development Software Handbook documents the design flow and language support in the Quartus II software. It explains how to improve and control your synthesis results with Quartus II synthesis options, attributes, and other features. It also discusses node-naming conventions and how to preserve nodes through synthesis.
Synplicity Synplify & SynplifyPro Support (PDF) This chapter of the Quartus II Development Software Handbook documents support for the Synplicity Synplify and Synplify Pro software in the Quartus II software, as well as key design methodologies and techniques for achieving good results in Altera devices.
Mentor Graphics Precision RTL Support (PDF) This chapter of the Quartus II Development Software Handbook documents support for the Mentor Graphics® Precision RTL Synthesis software in the Quartus II software, as well as key design methodologies and techniques for achieving good results in Altera devices.

Table 2 provides links to available training and demonstrations on Quartus II integrated synthesis and interfaces with third-party synthesis tools.

Table 2. Synthesis Training and Demonstrations
Title Description
Compilation
(Online Demonstration)

You will see how to make settings in a project, start a compilation, and view your results.

This is a 2.5-minute demonstration.

Using the Quartus II Software: An Introduction
(Online Course)

You will become familiar with the basic Quartus II design environment. You will learn about the steps of the basic FPGA design flow and how to use Quartus II software in the flow. You will locate basic functions in the Quartus II software user interface, such as where to create new projects and how to make pin assignments, and where to locate Quartus II software compilation output information. 

This is a 1.5-hour online course.

The Quartus II Software Interactive Tutorial
(Online Tutorial)

This interactive tutorial teaches you the basic components of the Quartus II design software including best-practice design flows, project management and design tools, and programming a device with your tested design. Each tutorial module has a Show Me, Guide Me, & Test Me component to first achieve an understanding of a design feature and then test you on what you have learned. You can navigate to any module in the tutorial at any time using the Table of Contents, and explore features at your own pace. 

This is a 4-hour online interactive tutorial course.

The Quartus II Software Design Series: Foundation
(Instructor-Led Course)

The Quartus II Software Design Series: Foundation
(Online Course)

You will create a new project, enter in new or existing design files, compile, and configure your device using the programmer to see the design working in-system. You will also enter basic internal and I/O timing constraints and analyze a design for these timing constraints using the TimeQuest timing analyzer. You will also learn how to plan and manage pin assignments and will discover how the software interfaces with common EDA tools used for synthesis and simulation.

This is a 1-day instructor-led course or 8-hour online course.

The Quartus II Software Design Series: Optimization (Instructor-Led Course)

You will learn advanced features of the Quartus II software that enable you to shorten your design cycle as well as improve your design performance and utilization. You will obtain your design goals in the area of performance, resource usage, and power consumption by using design strategies, HDL coding styles, and Quartus II software settings. You will also learn how to manage compilation times effectively. 

This is a 1-day instructor-led course.

Netlist Viewers Resources

Table 3 provides a link to available documentation on the Quartus II netlist viewers.

Table 3. Netlist Viewers Documentation
Resource Description
Analyzing Designs with Quartus II Netlist Viewers (PDF) This chapter of the Quartus II Development Software Handbook describes the user interface and features of the viewers and provides examples. The Quartus II RTL viewer, state machine viewer, and technology map viewer provide powerful ways to view your initial and fully mapped synthesis results during the debugging, optimization, or constraint entry process.

Table 4 provides links to available training and demonstrations on the Quartus II netlist viewers.

Table 4. Netlist Viewers Training and Demonstrations
Resource Description
Using the RTL Viewer and Technology Map Viewer to Check Synthesis and Fitting Results
(Online Demonstration)

You will see how to navigate in the RTL and technology map viewers and how you can use the viewers to debug design problems.

This is a 5-minute demonstration.

The Quartus II Software Design Series: Optimization
(Instructor-Led Course)

You will learn advanced features of the Quartus II software that enable you to shorten your design cycle, as well as improve your design performance and utilization.

This is a 1-day instructor-led course.

Rate This Page


  • Products
    • Quartus II
      • Basic Design Flow
        • Create Project
        • Make Assignments
        • Compile Designs
        • Analyze Results
        • Modify Settings
        • Assign Pins
    • SOPC Builder
    • MAX+PLUS II
    • ModelSim-Altera
  • Resource Centers
    • Overview
    • Installation & Licensing
    • Scripting
    • Board Design & I/O
    • Design Entry & Planning
    • Synthesis & Netlist Viewers
    • Incremental Compilation
    • Optimization
    • Power Management
    • TimeQuest Timing Analyzer
      • Clock Analysis
      • Exceptions
      • Collections
      • GUI Features
    • Classic Timing Analyzer
    • Simulation & Verification
    • On-Chip Debugging
    • HardCopy Design
    • EDA Tool Support
  • Software Resources
    • OS Support
    • Driver Installation
  • Download & Licensing
    • Download
    • Licensing
      • Licensing FAQ
    Please give us feedback
    Products | End Markets | Technology | Training | Support | About Altera | Buy Online
    Jobs | Investor Relations | Contact Us | Site Map | Privacy | Legal Notice
    Copyright © 1995-2010 Altera Corporation. All Rights Reserved.
    Altera Forum
    Altera
    Forum
    Twitter
    Twitter
    RSS
    RSS
    Facebook
    Facebook
    Flickr
    Flickr
    YouTube
    YouTube
    Email Updates
    Email
    Updates