Optimization Support Resources
Altera's Quartus® II software includes a wide range of features to help you optimize your design for area and timing. This page provides resources to help you with design optimization, physical synthesis, and the Design Space Explorer (DSE).
Quartus II software offers physical synthesis netlist optimization to optimize designs further than the standard compilation process. Physical synthesis helps improve the performance of your design, regardless of the synthesis tool used.
The DSE automates finding the set of options for best results in any individual design. DSE explores the design space of your design, applies various optimization techniques, and analyzes the results to help you discover the best settings for your design.
For resources on design optimization, refer to the following:
To search for known optimization issues and technical support solutions, use Altera’s Knowledge Database. You can also visit the Altera® Forum to connect and discuss technical issues with other Altera users.
For further technical support, use mySupport to create, view, and update service requests.
Design Optimization Resources
Design optimization can help you improve performance to reduce resource usage, close timing, and reduce compilation times. Table 1 lists the available optimization support documentation.
| Table 1. Optimization Support Documentation |
| Title |
Description |
| Area and Timing Optimization (PDF) |
This chapter of the Quartus II Development Software Handbook explains techniques to reduce resource usage, improve timing performance, and reduce compilation times when designing for Altera devices. |
| Analyzing and Optimizing the Design Floorplan (PDF) |
This chapter of the Quartus II Development Software Handbook describes how you can use the chip planner tool (and the timing closure floorplan for older devices) to analyze and optimize the floorplan for your designs. This chapter also explains how to use LogicLock™ regions to control the placement. |
| Engineering Change Management with the Chip Planner (PDF) |
This chapter of the Quartus II Development Software Handbook describes using the chip planner to implement engineering change orders (ECOs) for supported devices. |
| Netlist Optimizations and Physical Synthesis (PDF) |
This chapter of the Quartus II Development Software Handbook explains how the netlist optimizations and physical synthesis in Quartus II software can modify your design’s netlist and help improve your quality of results. |
| Design Space Explorer (PDF) |
This chapter of the Quartus II Development Software Handbook describes the DSE and how you can use it to obtain the best compilation results. |
| Synthesis and Netlist Viewer Resource Center |
Following recommended coding guidelines can be a powerful way to obtain good quality results. Refer to the Design and Coding Guidelines section in the Synthesis and Netlist Viewer Resource Center for more information. |
| Incremental Compilation Resource Center |
You can use incremental compilation to reduce compilation times and preserve results during optimization.
|
Table 2 provides links to training and demonstrations on the features and use of optimization resources.
| Table 2. Optimization Support Training Courses and Demonstrations |
| Title |
Description |
Optimization Advisor
(Demonstration) |
See a quick demonstration on the Quartus II software optimization advisor.
This is a 4-minute online demonstration.
|
|
The Quartus II Software Design Series: Foundation
(Instructor-Led Course)
The Quartus II Software Design Series: Foundation
(Online Training)
|
Learn how to use Quartus II software to develop an FPGA or CPLD. Create a new project, enter in new or existing design files, compile and configure your device using the programmer to see the design working in-system. Learn how to apply timing constraints to your design, and analyze your design using the TimeQuest timing analyzer, the static timing analyzer in the Quartus II software.
You will also learn techniques that help you plan your design and understand how Quartus II software interfaces with common EDA tools used for synthesis and simulation.
This is an 8-hour instructor-led course.
|
The Quartus II Software Design Series: Optimization
(Instructor-Led Course) |
Learn advanced features of Quartus II design software that will enable you to shorten your design cycle as well as improve your design performance and utilization. Use the incremental compilation flow and LogicLock regions in the Quartus II software to reduce compile times and preserve performance. Learn how to achieve required performance, resource usage and power consumption by using design strategies, HDL coding styles and Quartus II software settings.
You will also learn how to manage compile times effectively and how to use DSE to select optimal settings for full or partial designs.
This is an 8-hour instructor-led course.
|
|
Using the Quartus II Software: Chip Planner
(Online Course)
|
Learn about the chip planner tasks, layers, and views, and how to perform design analysis with chip planner. See how to view critical paths and physical timing estimates. You will also see how to use chip planner to perform power analysis and to view routing congestion.
You will also learn how to perform engineering change orders (ECOs) and to work with floorplan assignments.
This is a 1-hour online course.
|
Using Quartus II Software: Managing Design Changes with Chip Editor
(Online Course) |
Learn how to use chip editor in the Quartus II software version 4.0 to analyze and modify post place-and-route FPGA designs. You will also see practical examples of using chip editor for correcting minor design bugs and optimizing timing without having to recompile the entire design, therefore shortening the design turn-around time.
Starting with Quartus II software version 6.1, all the functionality of the chip editor is available in the chip planner.
This is a 1-hour online course.
|
| Design Space Explorer (Online Demonstration) |
This demonstration gives you an overview of the DSE tool.
This is a 4-minute online demonstration.
|
|
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