Release Notes For ModelSim Altera 6.1g Copyright 2006 Mentor Graphics Corporation All rights reserved. This document contains information that is proprietary to Mentor Graphics Corporation. The original recipient of this document may duplicate this document in whole or in part for internal business purposes only, provided that this entire notice appears in all copies. In duplicating any part of this document, the recipient agrees to make every reasonable effort to prevent the unauthorized use and distribution of the proprietary information. Aug 11 2006 ______________________________________________________________________ Product Installation and Licensing Information For brief instructions about product installation please visit the "install_notes" file in www.model.com. The install_notes file can be viewed at: [1]http://www.model.com/products/release.asp For detailed information about product installation and licensing see the ModelSim Start Here Guide. The manual can be downloaded from: [2]http://www.model.com/support/documentation.asp Release Notes Archives For release notes of previous versions visit the release notes archive at: [3]http://www.model.com/support/default.asp or find them in the installed modeltech tree in /docs/rlsnotes How to get Support This OEM product is supported by Altera Corporation * World-Wide-Web Support [4]http://www.altera.com/mySupport ______________________________________________________________________ Index to Release Notes [5]Key Information [6]User Interface Defects Repaired in 6.1g [7]Verilog Defects Repaired in 6.1g [8]PLI Defects Repaired in 6.1g [9]VHDL Defects Repaired in 6.1g [10]FLI Defects Repaired in 6.1g [11]VITAL Defects Repaired in 6.1g [12]SystemC Defects Repaired in 6.1g [13]Assertion Defects Repaired in 6.1g [14]Mixed Language Defects Repaired in 6.1g [15]General Defects Repaired in 6.1g [16]Mentor Graphics DRs Repaired in 6.1g [17]Known Defects in 6.1g [18]Product Changes to 6.1g [19]New Features Added to 6.1g ______________________________________________________________________ Key Information * The RedHat Enterprise Linux 4 is supported as of the 6.1b release. The support includes the following platforms: + 32-bit linux + 64-bit linux_x86_64 For a complete list of supported platforms see the Install Guide under the section Supported platforms. * The following platforms will be discontinued as of the 6.2 release: + Windows 98 + Windows ME + Windows NT 4.0 + Solaris 2.6 + Solaris 7 + AIX 4.3 * Solaris OS 10 is supported as of the 6.1a release. Solaris OS 10 support includes SystemC. However, cdebug is not supported. Solaris 10 has the following limitations: + In the OS, vt alarm is producing irregular and random beats between 20ms and 100ms. As a result, the profiler produces the error message, "Too few samples." To workaround this problem, add the following line to the file /etc/system and reboot the system: set hires_tick=1 This will produce consistent sample times. The minimum sample time will be 20ms. This problem has been filed as Sun CR 6290459 and will be fixed in a coming kernel patch. With the patch, the minimum sample time will be approximately 10ms, as in previous Solaris releases. + In rare cases, simulations using sockets via the FLI may hang the system and produce a messages like "nfs server array not responding" may be produced. This problem has been filed as Sun CR 6296698. + In Solaris 10, g7 is always reserved. Any PLI/FLI/DIP using g7 will break under Solaris 10. * The following platform changes are effective as of the 6.0 release. + The 64-bit simulator is supported on the AMD Opteron and compatible processors running 64-bit Linux (SuSE 9.0 (x86-64) or RedHat Enterprise Linux WS release 3) as the linux_x86_64 platform. The profiling feature is not supported in 64-bit mode. The 32-bit simulator for the linux platform may also be installed and used concurrently on these systems. + RedHat 6.0 through 7.1 are no longer supported. * You must recompile or refresh your models if you are moving forward from 6.0x or earlier release versions. See "Regenerating your design libraries" in the User's Manual for more information on refreshing your models. * Acrobat reader version 4.0 or greater must be used to read any .pdf file contained in version 5.5c or greater. * The HP-UX 10.20 platform is no longer supported as of the 5.7 release. The hp700 platform executables are built on HP-UX 11.0. Please note that in order for FLI/PLI shared libraries to be loaded and executed correctly by the hp700 version of vsim, they must be compiled and linked on HP-UX 11.0. * Beginning with the 5.6 release (on Windows platforms only), attempts to link in libvsim.lib or tk83.lib using the Microsoft Visual C++ linker version 5.0 will fail with a message similar to "Invalid file or disk full: cannot seek to 0xaa77b00". Microsoft Visual C++ version 6.0 should be used. * Beginning in the 5.8 release, SDF files compressed in the Unix compress format (.Z) are no longer supported, but the GNU zip format (.gz)is supported. Therefore, we only when read in compressed SDF files that are created with the GNU zip (gzip) extension. A file is not require to have a .gz extension, but it will error on files that have a .Z extension. * Support of SystemC has dependencies on both operating system versions and C++ compiler versions. The OS support is slightly different than the simulation environments OS support for designs without SystemC content. Also, 64-bit compilation is not supported for SystemC designs. Supported Operating Systems and C++ compilers: + RedHat 7.3 and greater, gcc 3.2 + RedHat EWS2.1/7.2 and greater, gcc 3.2.3 (simulation environment version 5.8b and greater) + Solaris 2,6, 7, 8 , 9, 10, gcc 3.3 + HP-UX 11.0 and greater, aCC 3.45 + Win32 XP and 2000, gcc 3.2.3 (Simulation environment versions 6.0 and greater) * The LE product does not support VHDL. However, it does support Verilog and SystemC. * CDEBUG compatibility information by platform. + On HP-UX 11.0, the built-in HP wdb 3.3 program is used as the underlying C/C++ debugger. In order to run wdb successfully, you must have installed HP-UX PHSS_23842, or a superseding patch. Without this patch installed, error messages will occur during CDEBUG startup. + On rs6000, gdb-6.0 works with gcc-3.2. Additionally, when creating shared objects, 'ld' (/bin/ld) should be used, not 'gcc'. This combination works with AIX-5.1. On AIX-5.1 use gcc-3.2-aix51. The native compiler /bin/cc is not compatible with gdb-6.0. * The vcom compiler default language has been changed from VHDL-1987 to VHDL-2002. To choose a specific language version: + select the appropriate version from the compiler options menu in the GUI, + invoke vcom using switches -87, -93, or -2002, or + set the VHDL93 variable in the [vcom] section of modelsim.ini. Appropriate values for VHDL93 are: o 0, 87, or 1987 for VHDL-1987; o 1, 93, or 1993 for VHDL-1993; o 2, 02, or 2002 for VHDL-2002. * Although the vlog compiler currently supports some SystemVerilog features, these extensions are not enabled by default because they require new language keywords that may conflict with identifiers in existing code. There are two ways to enable SystemVerilog features: the first is by using the -sv command line option and the second is by naming the source file with a ".sv" suffix. * The EM64T platform is supported as of the 6.0b release. The support includes EM64T machines loaded with Suse 9.1 OS or RedHat Enterprise Linux 3 Update 3 OS and the following linux configurations. + 32-bit linux + 64-bit linux_x86_64 FlexLM v8.2a (which is currently shipped in 6.0x) is not supported on an EM64T machine loaded with Suse 9.1 OS. * The 6.1 release will use the following licensing versions: FLEXlm v9.5; Mentor Graphics Licensing MGLS v2004.2 and PCLS 2004.328. CRITICAL LICENSING INFORMATION: For this release of the product, the FLEXlm licensing software being used is version 9.5. For floating licenses it will be necessary to verify that the vendor daemon (i.e., mgcld) and the license server (i.e., lmgrd) have FLEXlm versions equal to or greater than 9.5. The vendor daemons and lmgrd that are shipped with this release will be FLEXlm version 9.5. If the current FLEXlm version of your vendor daemon and lmgrd are less than 9.5 then it will be necessary to stop your license server and restart it using the vendor daemon and lmgrd contained in this release. If you use node locked licenses you don't need to do anything. * SystemVerilog Program blocks are now supported except for the $exit() task. * The default time unit for SystemC can be set using the "ScTimeUnit" variable in the modelsim.ini file. By default ScTimeUnit is set to 1 ns. The default time unit in SystemC can also be set using the sc_set_default_time_unit() function before any time based object like sc_clock or sc_time is created. * vlog,vcom and vopt command line options will be case sensitive similar to the vsim command line options. * Starting in the 6.1 release, the vsim -dpiexportobj option has changed behavior somewhat. This primarily affects win32 and rs6000 users. 1. You shouldn't put an extension on the object filename. That will be done for you automatically now. 2. There is no longer a need to add "-c -do 'quit -f'" to the vsim -dpiexportobj command line. The examples/systemverilog/dpi/simple_calls runtest.bat files have been modified to show the correct flow now. * Due to some bug fixes, some VHDL models compiled with 6.1b or higher will not run under 6.1 and 6.1a. These models will generate the error: # ** Fatal: (vsim-3274) Empty built-in function pointer (511). # Either this version of vsim is not compatible with the compiled # version of the libraries that were loaded or a required shared library # was not loaded. Please recompile the libraries with -refresh or make # sure you specify the required shared library to vsim. * The following lists the supported platforms: + win32aloem - Windows 2000, XP + sunos5aloem - Solaris 8, 9 + hp700aloem - HP-UX 11 + linuxaloem - RedHat 7.2 and higher. ______________________________________________________________________ User Interface Defects Repaired in 6.1g * Waveform printing now handles labels too large to fit into the waveform by replacing characters in the label with '...' or removing the label instead of scaling down the font for the label. * The waveform printing interface now handles sizes specified in cm correctly. * A WLF writer bug caused optimizations to inadvertently be disabled, in some cases, if a large number of signals (>50,000) was logged after time 0. This resulted in slower than expected Wave window drawing speed and potentially a vsim assertion. * A WLF dataset snapshot bug caused the snapshotting to become disabled under some circumstances. * A bug in the "dataset close" function in certain cases caused a crash if a virtual signal was currently displayed in the Objects window and the command dataset close -all was issued. * The Wave window crashed in certain cases if the window was closed while waves were actively drawing. * There were problems with the GUI "Customize" feature, such as the buttons were not added, errors were produced, or the U/I locked up. This feature is found under the Windows menu, or when using the commands apply_button_adder or _add_menu. * A memory leak caused the U/I to run out of resources and either hang or crash the simulator after multiple simulation runs during a single session. * Dragging a signal from the Source window to the Wave window took a very long time. * Selection of a non-active process in the Structure or Dataflow window in certain cases required excessive time as the Active Process window was populated. An example of this scenario is immediately after elaboration but before any run has been done when many Verilog "initial" processes would be scheduled. This time has been minimized. ______________________________________________________________________ Verilog Defects Repaired in 6.1g * An optimization of a "repeat (1)" statement under the default label of a case statement resulted in an internal error during compilation. * An inversion of an or-reduction expression (and other reduction operators) evaluated to incorrect results in some cases. * In certain cases the command coverage report -du did not have the correct data for Verilog registers. * vlog -source crashed in certain cases when attempting to print a source line with a warning or error message. * In the vlog compiler, a cache related to timing check condition expressions was not cleared correctly resulting in unpredictable behaviour in some cases. * Under certain conditions, the gate-level optimized cell evaluator ignored notifier register toggles fanning into always blocks. * When +multisource_int_delays and/or +transport_int_delays was specified with -v2k_int_delays or compiled SDF files, in simulating a design that had nets with large fanin and fanout, the SDF load times were very long. * When +grp_ntc_outputs was specified for vlog and +multisource_int_delays or +transport_int_delays was specified for vsim, some simulations looped infinitely. ______________________________________________________________________ PLI Defects Repaired in 6.1g ______________________________________________________________________ VHDL Defects Repaired in 6.1g * When compiled with -O1, individual association in a configuration's port maps incorrectly connected signals if the component port was an array and has different bounds than the actual associated with it. * If an alias to a type was declared in the same scope as the type was declared, the implicit operators for the type were incorrectly redeclared. This was a problem if the implicit operators were replaced with explicit versions. This caused the compiler to report ambiguous expressions. * An expression with a subexpression of an array type followed by a subexpression involving a short-circuit operation with array type operands in some cases resulted in the preceding subexpression having its value corrupted. ______________________________________________________________________ FLI Defects Repaired in 6.1g ______________________________________________________________________ VITAL Defects Repaired in 6.1g ______________________________________________________________________ SystemC Defects Repaired in 6.1g ______________________________________________________________________ Assertion Defects Repaired in 6.1g ______________________________________________________________________ Mixed Language Defects Repaired in 6.1g * Changes did not propagate on a forced or released Verilog I/O port that was connected to a VHDL I/O port. ______________________________________________________________________ General Defects Repaired in 6.1g * vcover with the merge argument crashed in certain cases. * The coverage save command produced duplicate information in the coverage save output file under some conditions. * The command vcd dumpports crashed for VHDL 'bit' type (this type is not supported - see the documentation for more information). * There was a problem with the coverage report and coverage save commands where design hierarchy regions were ignored if they had toggles coverage enabled and no other coverage metrics enabled. * There was a problem in vcover with the report option where condition and expression tables were missing from certain coverage reports. * Condition and expression data was missing from certain GUI coverage windows. * If vsim assertions were redirected to a file other than the transcript file (with the -assertfile command line option or the "AssertFile" modelsim.ini variable) and the assertion file grew to a size greater than 2GB, vsim crashed. * vcover with the options report -xml produced the wrong condition and expression statistics which was caused by the active count not including exclusions. ______________________________________________________________________ Mentor Graphics DRs Repaired in 6.1g * dts0100335166 - Modelsim crashing when using "vcd dumpports". * dts0100341584 - Verilog compilation is not able to handle >1000 modules in one vlog command. * dts0100335726 - Documentation not clear enough about coverage exclude -inst. ______________________________________________________________________ Known Defects in 6.1g * In code coverage, there is no way to exclude a condition or expression table row for the case of more than one table on a line and the table in question is not the first table on the line. * The add_menu command does not work for the Wave window. The work around is to use the [winfo toplevel $wave] command to obtain the correct widget pathname; for example: set wave [view -undock wave] set wavetop [winfo toplevel $wave] add_menu $wavetop "MyMenu" This work around is not required for future versions, but should not cause problems. ______________________________________________________________________ Product Changes to 6.1g ______________________________________________________________________ New Features Added to 6.1g * HDL source code pragmas have been added for individual code coverage metrics. This allows you to turn statement, branch, condition, expression and fsm coverage on and off independently using source code pragmas. To use it, add an additional argument to the coverage on or coverage off pragma using characters to indicate the coverage metric. This works for both VHDL and Verilog. (For toggle coverage, use the "coverage toggle_ignore" pragma.) For example: // coverage off sce turns off statement, condition and expression coverage, and leaves the other metrics alone. // coverage on bf turns on branch and fsm coverage, leaving the other metrics alone. * Added a -depth option to the coverage save -instance command that specifies the depth of hierarchy to save. The following example will save two levels of hierarchy, starting at /top/myinst. coverage save -inst /top/myinst -depth 2 myout.cov * Added a -filter option to the coverage save -instance command that will filter out excluded instances and everything below. * A feature has been added to coverage report to print the file name for the design unit in the toggle details section. To turn it on, you need to use coverage report -tfile. * SDF annotation support of setuphold and recrem timing checks using a combination of explicit condition arguments and implicit condtions on events were added.