Release Notes For ModelSim Altera 6.3g_p1 Aug 13 2008 Copyright 1991-2008 Mentor Graphics Corporation All rights reserved. This document contains information that is proprietary to Mentor Graphics Corporation. The original recipient of this document may duplicate this document in whole or in part for internal business purposes only, provided that this entire notice appears in all copies. In duplicating any part of this document the recipient agrees to make every reasonable effort to prevent the unauthorized use and distribution of the proprietary information. TRADEMARKS: The trademarks, logos and service marks ("Marks") used herein are the property of Mentor Graphics Corporation or other third parties. No one is permitted to use these Marks without the prior written consent of Mentor Graphics or the respective third-party owner. The use herein of a third-party Mark is not an attempt to indicate Mentor Graphics as a source of a product, but is intended to indicate a product from, or associated with, a particular third party. The following are trademarks of of Mentor Graphics Corporation: Questa, ModelSim, JobSpy, and Signal Spy. A current list of Mentor Graphics trademarks may be viewed at www.mentor.com/terms_conditions/trademarks.cfm. End-User License Agreement: You can print a copy of the End-User License Agreement from: www.mentor.com/terms_conditions/enduser.cfm. ______________________________________________________________________ Product Installation and Licensing Information For brief instructions about product installation please visit the "install_notes" file in www.model.com. The install_notes file can be viewed at: [1]http://www.model.com/products/release.asp For detailed information about product installation and licensing see the ModelSim Start Here Guide. The manual can be downloaded from: [2]http://www.model.com/support/documentation.asp Release Notes Archives For release notes of previous versions visit the release notes archive at: [3]http://www.model.com/support/default.asp or find them in the installed modeltech tree in /docs/rlsnotes How to get Support ModelSim Altera is supported by Altera Corporation * World-Wide-Web Support [4]http://www.altera.com/mySupport ______________________________________________________________________ Index to Release Notes [5]Key Information [6]User Interface Defects Repaired in 6.3g_p1 [7]Verilog Defects Repaired in 6.3g_p1 [8]PLI Defects Repaired in 6.3g_p1 [9]VHDL Defects Repaired in 6.3g_p1 [10]FLI Defects Repaired in 6.3g_p1 [11]VITAL Defects Repaired in 6.3g_p1 [12]SystemC Defects Repaired in 6.3g_p1 [13]Assertion Defects Repaired in 6.3g_p1 [14]Mixed Language Defects Repaired in 6.3g_p1 [15]Coverage Defects Repaired in 6.3g_p1 [16]General Defects Repaired in 6.3g_p1 [17]Mentor Graphics DRs Repaired in 6.3g_p1 [18]Known Defects in 6.3g_p1 [19]Product Changes to 6.3g_p1 [20]New Features Added to 6.3g_p1 ______________________________________________________________________ Key Information * The following lists the supported platforms: + win32aloem - Windows 2000, XP + sunos5aloem - Solaris 8, 9, 10 + linuxaloem - RedHat 7.2 and higher. ______________________________________________________________________ User Interface Defects Repaired in 6.3g_p1 * If the user set the environment to a region with transaction streams, then switched to another environment, ran for a while, and then switched back to the region with TR streams, the UI could crash. * In the Wave window, if a load format is issued and there is not enough room in the pane for the requested name/value column size, these columns were reduced to a minimum size, allowing all columns to be visible. If the Wave window was then undocked and ample space existed, the initial column widths requested from the load format were not considered. The format column widths for a load format are now retained and will be used once enough space exists. * Wave compare fails with SV record types. * The Compile Options dialog does not process options specified in the "Other Verilog Options" portion of the dialog box under the Verilog tab. The Verilog and SystemVerilog tabs have been combined into a single tab. The issue with the "Other options" entry box have been resolved. * Expanding a virtual signal containing slices created using the concat_noflatten switch sometimes caused the GUI to crash. * When hitting the break key twice the simulator could report the message: can't read "vsimPriv(profileState)" * The change command did not work on all fields of a packed struct. * The describe command showed no result for scope without trailing '/'. * The "Contains" toolbar is now enabled for the Memory tab. * Corrupted MPF (project) files could result in the simulator crashing. The simulator now detects the corruption, and properly reports the error. * The Memory toolbar now is provided in the Main window when memory data pane is in MDI. * The problem with double clicking in memory data pane when there is no data has been fixed. * PSL Cover directives print as busses. ______________________________________________________________________ Verilog Defects Repaired in 6.3g_p1 * Use of +delayed_timing_checks with modules having timing checks without explicit delay nets could result in an incorrect delay net delay solution. * The -vcdstim simulator option resulted in an elaboration crash in some cases if the design contained an array of instances. * Signal Spy system task calls, like $init_signal_spy(), could fail due to incorrectly generated paths in optimized designs where relative design object names were provided. * The scheduler dropped simulation events in an optimized design in some cases where always blocks were incorrectly executed before the simulation time was initialized to zero, and where the always blocks scheduled delayed events. * Bit Stream Cast and Streaming Operators involving dynamic arrays with no elements would sometimes result in spurious error of concatenation invalid for REAL or a memory failure. * Errors such as: "Error: (vsim-3043) test.v(6): Unresolved reference to 'j'" would sometimes be reported by vsim for the loop iterator, when a foreach loop was used in a task or function. * In some cases an incorrect optimization would result in bad values for an accumulating expression of the form "a = a + b" where "a" is 2-state and "b" is four-state. * In some forms of hierarchical and interface calls, a small signed actual expression would not be correctly sign extended when assigned to a wider unsigned formal. * In some cases involving parameterized class properties, incorrect errors regarding variables being "const" would be reported. * If both cell and instance clauses of a configuration applied to a given instance, the cell clause's liblist or use clause was selected. This selection did not produce the most specific match. The selection procedure has been revised to give preference to matching instance clauses. Warnings are produced when multiple instance and cell clauses are applicable to a given instance. * In some cases, calls to inherited non-static methods from a static method context would not be caught as errors and would result in an internal compiler error. * In System Verilog, the local and protected qualifiers were not being enforced when used with class constructors (the "new" method). * A reference to a 'struct' field within an 'always_comb' block, under certain circumstances, could result in a crash during elaboration, or in incorrect sensitivity for the block. * When an include file was used within a Verilog module and within a `protect / `endprotect block, vopt would incorrectly report an error. * When a parameter with a negative value was used to specify packed dimensions of a net port type in novopt mode, it resulted in a incorrect error such as: Index into 'net' is out of bounds. * Sometimes a pattern matching case statement caused the compiler to crash and gave a fatal error such as: ** Error: test.v(21): Internal error: ../../../src/vlog/vgenexpr.c(386) isImmedVal(vop) * Referring to a wrong name as a function call caused the compiler to crash with an error such as: Internal error: ../../../src/vlog/vrslvexpr.c(5743). * Annotation of INTERCONNECT delays to toplevel ports with -v2k_int_delays option (or compiled SDF) caused a crash. * Fixed incorrect behavior of optimized cells when if conditional expression is evaluated to X. The bad behavior occurred when the if conditional expression is evaluated to X, none of the "if" and "else" statements were executed. * To allow input of net type tri1 or tri0 in cell optimization, add the switch +nocheckINTRI. This switch is included in +nocheckALL switch. * Calling a system task or function with an argument that used an automatic variable for a bit-slice expression like "d[auto_var+:8]" generated an internal error. * Errors occurring at the end of one Verilog file may have resulted in error messages with incorrect data. * Using nested generate blocks could cause an elaboration crash in vopt mode in rare cases due an optimization problem. * Support reg register data type in always block trigger for cell optimization. * The 'next(key)' and 'prev(key)' methods on associative arrays are supposed to return the next/previous entry, even if the key given does not exist. Previously, these methods were failing (returning 0) in those cases. * Unknowns caused by timing check violations, could in some cases, get scheduled in zero delay rather using an existing specify path delay. * A parameter in a default statement of a clocking block can cause vopt to crash if there is no input or output in the block body. For example: clocking ckp @(posedge clk; default input #setup output #hold; input sel; endclocking * In some cases references to the 'rand_mode' method of an extended class caused an internal error during compilation. * Library search rules were not working correctly in some case for generate or arrayed instances. * Simulation of gate-level optimized cells with numerous conditional $width or $period timing checks could crash. * Beginning in the 6.3e release, a memory leak could occur when using a disable statement to exit a block containing the disable statement. The leak did not occur for code inside a task or function. * Using `resetall in a protected block used to generate the message: ** Error: prot.v(18): Error in `endprotect directive. Matching `protect directive not found. This is now supported. * If +acc=g was used to block optimizations involving parameters and a generate loop depending on parameters could have been otherwise optimized, hierarchical references into elements of the generate loop might fail to resolve at elaboration time. * When +acc flags were being applied to local scopes or through generates, variables were not getting preserved within the scopes. Similarly with +floatparameters when the heirarchy through generates was specified, sometimes we did not float the parameters appropriately. * Optimizations involving continuous assignments resulted in false errors from vopt such as: "Bounds of part-select into '(null)' are reversed". * System task $deposit now works when the target is encrypted. * Conversion of longint negative values to real would result in incorrect values. This issue has been fixed. * Gate-level optimized full timing simulations could hang or crash while running. ______________________________________________________________________ PLI Defects Repaired in 6.3g_p1 * Some cases of incorrect behavior when a VPI application canceled a Value Change Callback while within the callback routine have been fixed. * The TF routines (tf_putp, for example) failed to write system task arguments that were valid lhs concatenation expressions. * Per the LRM, "Arguments to PLI tasks or functions are not evaluated until an application requests their value." In 6.3, systf arguments were incorrectly being evaluated during the vpi_scan() process. There are still occasions when systf arguments are evaluated as a result of a VPI action other than vpi_get_value(). This particularly applies to objects that are selections, as the evaluation is sometimes necessary to determine the selection information. * This release note is a reminder that there is no standardized definition of access to System Verilog objects via the deprecated ACC PLI. Usage of ACC on System Verilog designs is strongly discouraged for this reason; the tool makes no behavior or consistency guarantees across releases. A minor change to actual behavior has been made in this area, to further tighten filtering of System Verilog objects from ACC iterations. ______________________________________________________________________ VHDL Defects Repaired in 6.3g_p1 * An optimization of a process that modeled an edge sensitive flip flop, where the clock was an indexed expression and the index was a globally static value gave incorrect results. This happened, for example, in the incremental flow when the process was part of a for generate loop and the index value was the for generate loop variable. * Standard package "textio" READLINE, for some long lines in a file, would sometimes return a string of the wrong length. * vsim crashed after one or more restarts were done. * Additional types of signal assignments are now being optimized. * A sequence of consecutive signal assigments to an array signal from a package which has more than one assignment to one or more of the elements was being executed in the reverse order. ______________________________________________________________________ FLI Defects Repaired in 6.3g_p1 * The shared libraries associated with foreign subprogram were not reloaded when a restart was done. ______________________________________________________________________ VITAL Defects Repaired in 6.3g_p1 ______________________________________________________________________ SystemC Defects Repaired in 6.3g_p1 * The W_BEGIN, W_END and other watching macros are removed from the sc_macros.h SystemC header file. The watching function has been removed in SystemC 2.2. * Concatenation of sc_uints into a sc_biguint was giving incorrect values. * sccom supports files with .CPP extension. * sccom -link issue on RHEL5 on AMD 64-bit platforms is fixed. ______________________________________________________________________ Assertion Defects Repaired in 6.3g_p1 * The assertion count command now returns a "No matches" warning if the given path does not contain any assertions. This is to match the behavior of other commands like coverage report -asserts. The command used to return a hard error that would cause "do" scripts to terminate if not handled. ______________________________________________________________________ Mixed Language Defects Repaired in 6.3g_p1 * A VHDL design unit instantiated within a Verilog generate scope resulted in false (or missing) port connection error messages, possibly in unrelated instantiations. * Annotation of 2 (or more) SDF files, to instances that have escaped identifiers in the hierarchical pathname, caused a crash. * vopt crashed when accessing items within a black-boxed design unit and the design was mixed-language. * If a Verilog configuration has an instance clause specifying a VHDL design, and an associated use clause specifying a different name for the entity, vopt and vsim would not attempt to load the renamed entity. * The '!' operator was not supported inside actual expressions in while binding to VHDL target scopes. * An SDF annotation bug that manifests in mixed language scenarios similar to the following was fixed. A Verilog module is instantiated under a VHDL top level. The Verilog module has a $sdf_annotate statement. If the simulation is run in vopt mode the PORT and INTERCONNECT delays should be annotated in the v2k_int_delay mode, because the SDF file gets automatically compiled in the vopt flow. The PORT and INTERCONNECT delays were not being annotated in v2k_int_delay mode. ______________________________________________________________________ Coverage Defects Repaired in 6.3g_p1 * When an GamePlan testplan imported by xml2ucdb contained scopes with multiple types of child scopes (for example, a Feature containing both Property and Coverage items), the auto-numbering was done without respect to the scope type and, thus, did not coincide with the section numbering within the GamePlan utility. * Instance Coverage window was not showing instances having only toggle coverage data. * Missed Coverage window was showing expressions even if all the missed rows are excluded. * Fixed the crash in FSM extraction while accessing index expression and record expression. * The maximum number of UDP truth table rows allowed in a code coverage condition or expression has been made user configurable. There are now entries in the vcom and vlog sections of the modelsim.ini file for "CoverMaxUDPRows". The default is now 192. (For 6.3e and earlier the max was 192; for 6.3f the max was 256). There are also command line override options for vcom, vlog and vopt: -maxudprows . Increasing the number of rows will include more expressions for coverage but increases the compile time. Sometimes the compile time increase is quite dramatic. * Support has been added for code coverage pragmas of the form: // VCS coverage on // VCS coverage off * When a Verilog continuous assignment has a very complex right hand side, sometimes the compiler would convert the statement to an always block containing various kinds of case and if statements. When code coverage was on, modelsim would try to do code coverage on these internal statements, resulting in code coverage reports that didn't make sense, because these internal statements were not in the original source code. Code coverage is now automatically turned off for these internal statements. * The coverage report command failed when states and transitions of a FSM are in different source files. * Incorrect branch coverage counts were displayed in the Source window in viewcov mode on Solaris platforms. ______________________________________________________________________ General Defects Repaired in 6.3g_p1 * The tools vmap, vopt, and vcover have problems locking files on disk for update when the file is located on a Samba file system (SMBFS) or Common Internet file system (CIFS). These locking issues have been resolved. * It was possible to create more than one instance of the same transaction stream. * A race condition could lead to WLF logging data being corrupted leading to a crash. The frequency of the issue increased with 6.3f. The race condition has been corrected. Corrupted files can sometimes be displayed using -wlfnopt option. * Memory profiler reported incorrect values. * vopt reports an error (vopt-38) when optimizing a protected module in an archive library (vlib -archive). The error is benign and does not effect the results. * This issue only effects Windows platforms. After issuing a restart command, non-existent processes were created (similar to zombie processes on UNIX/Linux). The number of process would grow with each restart and would remain until the simulator was closed. This created a handle/resource leak. These process are now properly closed. * The wlfman filter utility could crash or generate incorrect optimized data if the begin time (-b ) was non-zero. * vsim was not giving a proper error message for cases where non-existent paths were passed to $signal_force function. * $init_signal_driver was not correctly propagating the initial value 'Z' to bit-selects for some cases. * vsim was crashing for some cases when an incorrect path was provided with a $init_signal_spy function call. * Retroactive child phase transactions were not recorded properly in the WLF file: This is fixed. All transaction start and end events now correctly record with iteration zero. An additional check for illegal phase transactions has been added. ______________________________________________________________________ Mentor Graphics DRs Repaired in 6.3g_p1 * dts0100426767 - SystemC v2.2 watching() removed W_BEGIN, W_END, W_DO, W_ESCAPE macros still there? * dts0100456794 - (Request for) filtering of memory view. * dts0100467191 - SignalSpy segfaults under certain conditions. * dts0100471244 - Describe command shows no result for scope without trailing /. * dts0100473866 - Verification Management, Tracker, weight 0 --> 100 % coverage and green. * dts0100475416 - prev() and next() functions not working on System Verilog associative arrays. * dts0100475434 - Wave window layout not always responds to saved wave.do file. * dts0100476235 - Wrong simulation result for -novopt inside FOR GENERATE -- correct value if -vopt is used. * dts0100479206 - Optimization error. * dts0100479287 - Viewer crashes frequently. * dts0100480081 - Verilog PLI: vpi_scan() unexpectedly invokes calltf routine. * dts0100480285 - Expanding virtual signal causes a crash. * dts0100480365 - Missed Coverage window does not reflect exclusions in viewcov mode. * dts0100480647 - Branch coverage numbers wrong in the GUI on Solaris sunos5 and sunos5v9. * dts0100481406 - crash using vcdstim with design that have arrays of instances. * dts0100481718 - vsim doesn't select the most specific instance/cell clause in a Verilog configuration. * dts0100481739 - The `LENGTH VHDL attribute does not returns the correct line length for lines longer than 1121 characters. * dts0100481959 - Problem concatenating two sc_unit<64> values to a sc_biguint<128>. * dts0100482025 - Interface instantiation below a module instantiation causes Fatal error (vsim-3365). * dts0100482127 - vsim crash zooming out on waveform. * dts0100482654 - Crashes with vsim 6.3 and SDF files. * dts0100482713 - Fails to load protected include file. * dts0100482729 - sccom will not compile files with .CPP extension, have to change to lower case .cpp to pass compilation. * dts0100482916 - vopt-38 error about archived library not containing .dbs file. * dts0100483012 - Error in init_signal_spy with vopt. * dts0100483276 - Very long compile times with 6.3f and coverage. * dts0100487278 - Please add variable to modelsim.ini to increase/decrease row values for coverage. * dts0100483296 - # delay greater than 4 hangs the simulation. * dts0100483402 - SDF annotate simulation do not specified the delay on vopt mode. * dts0100486903 - Bad pointer/access type passed to memory subsystem. * dts0100488599 - vopt bbox doesn't resolve references through VHDL (2-step flow does). * dts0100489065 - Instance coverage pane in simulator is empty even though instance specific coverage exists. * dts0100489730 - Crash when loading an optimized design. * dts0100489823 - Elaboration Seg Fault. * dts0100490363 - Crash with 2 SDF files with "\". * dts0100490657 - sccom -link fails on Linux RHEL5 AMD 64-bit. * dts0100490877 - Coverage report includes invalid reference to case branch coverage. * dts0100491599 - Crash when attempting to report a corrupted MPF file. * dts0100492061 - Viewing merged UCDB file causes crash. * dts0100492187 - Profile report example uses -hier option. * dts0100492583 - vopt crash in 6.3e and 6.3f. Simulation runs fine in 6.3c/d. * dts0100424846 - PSL Cover directives print as busses unlike other waveforms including Assert directives. * dts0100492121 - SV child transactions not displayed correctly in Wave window. * dts0100488506 - Different simulation results between 6.2d and 6.3f. * dts0100482987 - VHDL port vector of length one causes crash in 6.3e and wrong results in 6.3f. * dts0100482026 - Simulator does not allow Range for array of interfaces to be specified in format [variable:0]. * dts0100492270 - $deposit doesn't work in encrypted code. ______________________________________________________________________ Known Defects in 6.3g_p1 * Syntax highlighting may not function properly in the Source window (all the source is shown as plain text). You can fix this problem by editing ~/hte/v2_38/hte.ini (where ~ represents your "HOME" directory) and deleting the line that says: languages=cxx tcl verilog vhdl XML PSL * The viewcov mode version of "coverage clear" has a known difference in behavior compared to the vsim mode version. In the viewcov mode version, clearing coverage data in a design unit instance does not affect the coverage data for that design unit, itself. Also, if you clear coverage data in a design unit, all instances of that design unit are not affected by that operation. In vsim mode, the data is more tightly linked such that one operation affects the other. In viewcov mode, if you want to have correct data correlation between instances and design units, then you need to clear both instances and design units. * The simulator will hang if it tries to create a WLF file while running on a Linux 64-bit operating system from a working directory which does not support large files. One common instance of this is executing an add wave command, when the working directory was created under an older 32-bit Linux OS. This is a Linux operating system bug and cannot be fixed by the simulator. A workaround for release 6.3 and above is to execute the simulator with command line option -wlfnolock. * Users should be mindful of enabling both performance profiling and memory profiling at the same time. Memory profiling requires much overhead process, and it can skew the results of the performance profiling data. * On certain (RedHat) Linux Operating System versions the "-restore" feature occasionally fails. This is due to the memory allocation security (anti-hacking) feature of Linux. RedHat Enterprise release v.3 update3 was the first version to have this security feature. In these Linux releases two consecutive program invocations do not get the same memory allocation foot-print. For the "-restore" feature the simulator relies on having the same memory allocation foot-print. Users are advised to re-try this feature a few times as on average 3 out of 5 attempts are successful. In recent Linux versions, an override for this anti-hacking feature is provided. Please use it at your own discretion. * In code coverage, there is no way to exclude a condition or expression table row for the case of more than one table on a line and the table in question is not the first table on the line. * Support of debugging C code during a quit command was disabled on Windows. The corresponding C Debug command cdbg stop_on_quit was also disabled on Windows. * Specparams can be learned during the learn flow, but cannot be found on consumption. The workaround is to use full +acc deoptimization. * Attempting to traverse from an unnamed VPI typespec handle to an instance or a scope will result in a crash. * There are some limitations related to coverage exclusions: + Toggle exclusions are not supported in viewcov mode yet. + Exclusion report on toggles are not supported in both vsim and viewcov mode. * Concatenations and bit slices are not yet supported for System Verilog clocking blocks. * On Red Hat Enterprise Linux release 5 platform, If SIGSEGV signal occurs during the simulation and if CDEBUG is on, C-debugger traps the signal, and when continued, vsim gets terminated right away, instead of exiting with proper error status. * vlog will now print an "unsupported" error message for nested design-units, as this feature is not fully supported in 6.3. This error may be suppressed using the -suppress 2230 command-line options. * DU/View named with an extended identifier is not supported. ______________________________________________________________________ Product Changes to 6.3g_p1 * SDF annotation of RECREM or SETUPHOLD matching only a single setup/hold/recovery/removal timing check will result in a warning message. * The +acc switch of vopt has been enhanced to accept a 'q' specifier, which enables access to VHDL variables and generics. * If you use the GUI virtual signal/function command with "-install /", the signal will no longer be installed at the real context tree root, in which case it may be inaccessible, and certainly not observable in the objects window, but will now be installed in the top context of the first top-level design unit. * Nested XML testplan import (importing one testplan from inside another testplan) has been enhanced to support cross-format nesting. Previous issues with nesting an auto-numbered testplan inside an explicit-numbered testplan have been resolved. In particular, the following limitations are lifted: + Parameter inheritance now works correctly. + An explicit-numbered child testplan no longer has to be numbered to match the parent section. + Auto-numbered child testplans will now be numbered to match their parent section. * XML Testplan Import: The behavior of the "-title" and "-tagprefix" options has been clarified in light of the nested testplan enhancement: + For the top-most testplan, if "-title" is not set, the basename of the input XML file is used. + For the top-most testplan, if "-tagprefix" is not set, the "-title" value is used. + For nested testplans, neither option has a default (ie: if not set, they remain unset). Local (child) tags are only generated if the "-tagprefix" is set for the child testplan in question. * HTML Coverage Report: The "Coverage by Linked Item" table (on testplan scope summary page) has been significantly enhanced. The instance column now indicates the enclosing HDL scope for branch, condition, and expression coverage; the string in that column is a link pointing to the detailed coverage information for that item; and a column containing the filename and line number of the coverage item has been added. * The HTML coverage report has been enhanced to supress the coverage summary page for scopes which have no coverage (either because the source was not instrumented or was later excluded). In most cases, the scope will remain in the navigation tree but will be grayed-out (and not linked to a coverage summary page). In the design tree, if a scope and all it's children have no coverage, the children are dropped from the tree (testplan scopes are never dropped). * There have been some changes to the learn flow. Some performance issues have been addressed, including reducing the information learned during an SDF back-annotation phase. * File locking for UCDB merge: We support a cumulative merge (vcover merge out.ucdb out.ucdb in.ucdb). Such merge requests may occur simultaneously from various platforms in a networking environment. In order to avoid corrupting cumulative coverage results, merges of UCDB files are serialized. "out.ucdb" is only written by a single process at a time. + Creation of lock files whose purpose is to signal by their presence that a UCDB is locked for writing. + Operations are atomic. When creating the lock file, the process verifies that it does not exist and then creates it, but without allowing another process the opportunity to create it in the meantime. + The lock is advisory. Processes which intend to modify a UCDB file, by convention, check for locks to coordinate access to that file. The system fails if this convention is ignored. + There is a back-up file mechanism within vcover merge that, when optioned for, saves a back-up of the merge output before merging and can, when optioned for, automatically restore the back-up in case another process has its lock broken. + When blocked on a lock: o We print out "Waiting for lock..." messages every so often and let the user explicitly break the lock if they think it safe. o We produce a message similar to: "User Bilbo on machine Frodo has had the lock for 16 days". o Retry attempts will occur every 10 seconds. o Blocked messages will repeat about every 3 minutes. + The lock is released after a time-out period: o This cannot inadvertently time-out. Cannot be broken if a process is starved simply because others get in first. Time-out is only for the case where a single process takes too long. o The time-out period is user-configurable. o When a time-out condition occurs, the process timing out will be sent a "kill" signal. * The Verilog front-end now preserves block comments defined in the macro body through the macro substitution process. * The vsim '-assertfile ' switch now only applies to assertion (VHDL/SVA/PSL) messages issued by the tool. Use the vsim '-errorfile ' switch to redirect non-assertion tool messages into the specified file. To retain the tools previous behavior, set the environment variable MTI_ASSERTFILE_COMPATIBILITY to any value. This environment variable may eventually be deprecated. In the modelsim.ini file, all AssertionFormat variables have been renamed as MessageFormat variables. The MessageFormat variables are valid for both assertion and non-assertion tool messages, as before. For backward compatibility the AssertionFormat variables will continue to be supported. * The restart command will reload the current dataset if the current dataset is not the active simulation ("sim"), in effect acting just like a restart of a simulation. See the dataset restart command below under "New Features". * The XML Testplan Import configuration file (xml2ucdb.ini) has been moved from the product directory to a sub-directory, vm_src, directly below the product directory. * The ucdb2html utility has been removed from the release. The HTML report functionality had been integrated into vcover for 6.3 (see vcover report -html). * Due to changes required for resolution of product defects, the generated names of specializations of parameterized classes could be permuted. For example, if a name such as "C::C__2" was previously used for "C#(int)" and "C::C__3" was used for "C#(logic)", the names might be exchanged. The conditions under which name permutation could occur are based on internal details of how specializations are matched and are not directly correlated to source descriptions. * The default action for the command onbreak has changed from "pause" to "resume". This will only impact dofiles that do not currently contain any onbreak commands. The "pause" action causes the macro file to stop executing and issues a "Paused" prompt to allow interactive debugging of the macro file. The resume command continues the execution of the macro file at the point of the break. The result of this change in default value will affect macro files without an onbreak command so that those files will continue executing after hitting a break point. If the old behavior is required, then it will be necessary to add the command onbreak pause at the beginning of the macro file. * The default collapsed mode for VCD output from the vcd dumpports command has changed from not collapsed to collapsed. The specific change was to the line in the modelsim.ini file: "DumpportsCollapse = 0". For 6.3, this was changed to: "DumpportsCollapse = 1". To get the old non-collapsed format, change this setting back to 0 in the modelsim.ini file. * Starting in 6.3 concatenations are no longer treated as 'assignment patterns'. Previously, the simulator attempted to detect these cases and produced the following warning: You should use "'{" to specify this literal. Now we will print errors, as in the following example: int a[3:0] = {default:0}; int b[1:2] = {32'b1, 32'd2}; ... ** Error: test2.sv(31): Can't use named concat. literals here. ** Error: test2.sv(31): Illegal concatenation of an unsized constant. ** Error: test2.sv(31): Cannot assign a packed type to an unpacked type. ** Error: test2.sv(32): Cannot assign a packed type to an unpacked type. * Previously, an attempt to print a memory using $display displayed nothing, while $display of other unpacked types (such as structs and dynamic arrays) did produce output. In 6.3, we will now print an elaboration error, #8323, for all such constructs (which are illegal). This error may be suppressed. To print unpacked data, we have added the "%p" and "%0p" format specifiers. The former prints the data in the form of a legal "assignment pattern", while "%0p" prints in a shorter format. * Wildcard indexed associative array can no longer be used as a foreach array. * The IEEE Std 1800 has approved an important restriction to packages. With the new rules, packages are not permitted to refer to compilation unit items. An example of such of reference is the following small design: typedef int T; package p; T foo; endpackage Packages may depend on other packages so compilation unit declarations that packages need should be refactored into separate packages. For example, the previous design should be changed to a form similar to the following: package shared_types; typedef int T; endpackage package p; import shared_types::*; T foo; endpackage It is also important to note that "import" statements immediately before a package declaration are compilation unit imports and not imports into the subsequent package. With the new rules, the package references may not look into such an import. For example, the following approach will no longer work: package shared_types; typedef int T; endpackage import shared_types::*; package p; T foo; // cannot refer to T since it is imported into // the compilation unit, not into the package endpackage The new rules are now being enforced. Designs must be refactored so that packages do not refer to anything in the compilation unit. * Version 6.3d includes the v2.1 Mentor Graphics Documentation System, which includes the following components: InfoHub -- A browser-based directory that provides links to all your locally installed documentation. The InfoHub also provides a search interface, from which you can search across all your locally installed documents. The search interface also enables you to submit a search directly to SupportNet. The InfoHub provides access to User and Reference manuals and Tutorials, delivered in both HTML and PDF formats, and Release Notes, delivered in text format. PDF Bookcase -- A PDF file that provides links to the PDF documentation if you cannot use an HTML browser. Improvements to the v2.1 Mentor Graphics Documentation System include the following: Search changes -- Improved search time, multiple keyword support, search ranking icons, results filtering by book or topic, and improved accuracy of results. Search and content scopes -- A new My Search Scope option lets you define a custom set of books to search. Global index improvements -- improved viewing speed and collapse/uncollapse of "like" terms. Getting Started movie -- provides an overview of all the features of the InfoHub and Mentor Graphic Documentation System. You can view the Getting Started (Movie) from the Quick Tips menu located in the lower left-hand corner of the InfoHub. Font size -- increase or decrease the default size of the font by using the new triple "A" icon in the header. * The vopt +acc=g option has been replaced by the +floatparameters option(Verilog designs) and the +floatgenerics option (VHDL designs). Both +floatparameters and +floatgenerics accept the same [+][.] syntax accepted by +acc. Use +floatparameters and +floatgenerics to instruct vopt not to lock down values of parameters and generics during optimization. The parameters and generics will be left "floating", and thus capable of accepting modified values via the vsim -g and -G options. +floatparameters and +floatgenerics may have adverse effects on performance in some cases. * The vopt +acc=m option has been changed such that it no longer preserves primitive instances. Primitive instances are now preserved by using the new +acc=u option. * The VoptCoverageOptions variable has been removed from the modelsim.ini file. vopt optimizations for coverage are now controlled by the CoverOpt modelsim.ini file variable and the -cover command line option. * The -coverage option to vopt is no longer needed. vopt will automatically detect whether any of the source files were compiled with a -cover option, and will adjust its optimizations accordingly. Also, if you give a -cover xyz option to vopt, it will be logically OR'd with any -cover abc option given to an individual source file when processing that source file. In addition, if you compiled some source files with coverage on, you can force coverage off by giving vopt the -nocover option. This allows you to control whether coverage is on or off at vopt time instead of having to recompile individual source files. * The pathname reported by the simulator and User Interface for items inside SystemVerilog packages is incorrect. A path separator ('/') was used instead of the language correct package scope separator ('::'). * The recording of attributes for transactions has changed. Previously, any attribute recorded on a transaction was not only added to every transaction on that same substream, but to all parallel transactions and the transactions on their substreams as well. Now, any attribute recorded on a transaction is still added to every transaction on that same substream, but is no longer automatically added to every parallel transaction and the transactions on their substreams. Typically, all transactions on a given stream (and all of it's parallel substreams) have the same set of attributes, and for that case, there will be no difference due to this change. * Changes for coverage exclude command: + Replace the option -instance with -scope to accommodate more scope types like generate block. + Transition names are used with the option -ftrans instead of transition id's. The new syntax is: [-ftrans + | all] where transition_name is specified as -> . + State names are used with the option -fstate instead of state id's. The new syntax is: [-fstate + | all] + A new option -else is added to exclude the else part of every if-branch specified in the line range. Note that the line number for the else-branch is where the if-branch appears. + Recursive exclusion for a scope is supported. To recursively exclude a scope, -scope is specified together with -r. + -scope and -du are supported with -togglenode. * The UCDB bin name for if-branch is changed from 'true_branch' to 'if_branch'. * The simulator has been improved to recognize and maintain Verilog escaped identifier syntax for all Verilog escaped identifiers. Previously such identifiers were converted to VHDL-style extended identifiers, and then appeared as VHDL extended identifiers in tool output and CLI commands. Starting in 6.3, all default Verilog escaped object names inside the simulator appear identical to their names in original HDL source files. Sometimes in mixed language designs, hierarchical identifiers might refer to both VHDL extended identifiers and Verilog escaped identifiers in the same fullpath. For example: /top/\VHDL*ext\/\Vlog*ext /bottom top.\VHDL*ext\.\Vlog*ext .bottom (depending if the HierPathDelim variable is set to '/' or '.') Any fullpath that appears as user input to the tool (e.g. on the vsim command line, in a .do file, on the vopt command line, etc.) should be composed of components with escape syntax appropriate to their language kind. A modelsim.ini variable called "GenerousIdentifierParsing" can control parsing of identifiers input to the tool. If this variable is set (it is set by default now), either escape syntax to be used for objects of either language kind. This can be helpful to maintain compatibility with older do files, which often contain pure VHDL extended identifier syntax, even for escaped identifiers in Verilog design regions. Note that SDF files are always parsed in "generous mode". SignalSpy function arguments are also parsed in "generous mode". On the vsim command line, the language-correct escape syntax should be used for top-level module names. Using incorrect escape syntax on the command line will work in the incr flow, but not in vopt. This limitation may be removed in a future release. * If an invalid end time is specified when recording the end of transaction, a warning is still issued but the current simulation time is used as the transaction end time instead of the transaction start time. * The format of the library contents file (_info file) has been changed for the purpose of improved compiler performance. The new format is not backwards compatible with previous releases. Consequently, any attempt to refresh or recompile a 6.3 library with an older release will result in an error similar to the following: ** Error: (vcom-42) Unsupported ModelSim library format for "./work". (Format: 3). Converting the library back to an older release requires that you remove the library and rebuild it from scratch. Or, if you are converting back to a 6.2 release only, then you can convert the library format to the 6.2 format and then freely refresh back and forth between 6.2 and 6.3 releases. Use the 6.3 version of vlib to convert the format to the 6.2 version using the -format option. For example: vlib -format 1 work The format version for pre-6.3 releases is 1, while the format version for 6.3 is 3. Format version 2 is related to libraries created with the -archive option and should be avoided when specifying the vlib -format option. * The XML Testplan Import Utility (xml2ucdb) was enhanced and the command-line and configuration parameters were re-named for consistency. The following changes were made: 1. Command-line 1. Added a -verbose option to show testplan hierarchy and design mapping. By default, the utility is a lot less noisy than before. 2. A -ucdbfilename option has been added to remove the order-dependence of the files on the command line (the original syntax is still accepted). 3. The command-line arguments are now order-independent. 4. Any -format option found on the command line is processed first and other extraction parameters found on the command line act as overrides on top of the parameters found in the configuration file. 5. The same parameter names are used both on the command line and in the configuration file. 6. The -tagseparators option, when used on the command-line, applies only to the taglist parameters specified on the command line (see below). 2. Configuration file 1. Added "datalabels" parameter to support user-defined embedded data labels. 2. The following parameters have been re-named for consistency. In all cases, the former name is still recognized: 1. start => starttags 2. stop => stoptags 3. exclude => excludetags 4. description => descriptiontag 5. sectionitem => sectiontags 6. dataitem => datatags 7. testitem => titletag 8. coveritem => linktag 9. coverattr => linkattr 3. The "Tags" field name in the "fieldnames" and "fieldlabels" parameters has been renamed "Link". The former name is still recognized. 3. Behavior 1. The UCDB tags used to link testplan sections to coverage items now has the contents of the "title" parameter prepended. Lacking that, the basename of the XML input file is used. 2. The "startsection" parameter now reflects the initial section number for each level of hierarchy (auto-number mode only). 3. Data capture is no longer enabled from the start of the document in auto- number mode. An element matching "starttags" or a section number matching the "startstoring" parameter is required to enable data capture. * If the PATH column value is set to "-" it will be ignored (this is useful for the PATH-per-LINK case where one of the LINK values doesn't need a PATH). * XML Import (xml2ucdb) now supports a "Path" column to direct testplan link item matching to a specific region of the design. In addition, a path may be prepended onto any CoverGroup, CoverPoint or Cross link item. For CoverPoint, CoverGroup, and Cross link items: + If the contents of the Path column are non-blank, the Path information will be used as the value of the -path option to the tag command and the trailing component of the Link column will be parsed as usual and used to match the cover item. Any path added to the string in the Link column will be ignored. + If the Path column is not used or is left blank, and a path is prepended onto the string in the Link column, the prepended path will be used as the value of the -path option on the tag command. For CoverItem, Assertion, or Directive link items: + If the string in the Link column starts with a path separator character, the Link string is used as the value of the -path option in the tag command and no other tag command option is used. + If the string in the Link column does not start with a path separator (in other words, is not a full path), and the contents of the Path column are non-blank, the Path string is used as the value of the -path option and the Link strung is used as the value of the -match option on the tag command. + Otherwise, the Link string is used as the value of the -match option on the tag command and no path is specified. For all other link item types, the contents of the Path column are ignored. Note: If the Path column for a given link item is the literal string "-", the Path column is ignored for that link item only. * XML Import (xml2ucdb) now supports test data record tagging. If the Type column for a given link item is "Test", the contents of the Link column will be used as the value of the -testrecord option on the tag command associated with that link item. * XML Import (xml2ucdb) now supports a -stylesheet option ("stylesheet=" in the INI file). This option points to an XSL transformation stylesheet which is applied to the imported XML file prior to extraction. * XML Import (xml2ucdb) now supports XML files generated by Jasper's GamePlan testplan utility. Use the -format GamePlan option. * Use of the "analog" format within the Wave window has been made easier by adding support for the use of -min and -max to control waveform scaling (the old method required use of "offset" and "scale"). * Font Changes The way fonts are used and configured in the product has changed. There are now 5 configurable fonts in the product: menuFont, textFont, fixedFont, treeFont, and footerFont. These fonts are used by all windows and are customer configurable using the Edit Preferences dialog box. The previous method of configuring fonts is no longer used and the preference variables will be ignored. The Source window will continue to use it's own font setting as that window shares the font preferences with other products that use the DesignPad text editor. For current customers upgrading to 6.3b and later releases that have set up customized font preferences, these preferences will have to be manually configured for the new fonts, otherwise the product will look and behave just the same. * A change to licensing for this release eliminates extraneous entries in the license server log file that were the result of an availability check for a license feature. There used to be a license checkout line (i.e., OUT) followed by a license checkin line (i.e., IN) with 0 time duration each time the application checked on the availability of a license to decide whether to attempt the actual checkout of the license. * The vcd limit command has been changed adding support for a file size limit greater than 2 GB. The size argument now excepts a unit specifier. The default unit remains as bytes. An optional suffix of either KB, MB or GB specifies the units in which the size should be interpreted. For example: vcd limit 6GB or vcd limit 400MB * Taglists (used as data extraction parameters) may now include a subset of the XPath syntax to identify elements not only by tag name but also by the contents of attributes attached to said elements. This pseudo-Xpath syntax only handles "=" and "!=" and can only examine the attribute values attached to the element being compared. Moreover, only one attribute comparison may be performed. For example, the following extraction parameter: "-starttags Worksheet[@ss:Name=Sheet1]" will match the following element in the incoming XML: ... but will not match the following element: ... * The behavior of several extraction parameters in the XML Import utility has been clarified to allow various parameters to work more independently. The affected parameters are: starttags, stoptags, excludetags, and startstoring. * The change command can now be used to modify local variables in Verilog tasks and functions. * The profile UI has been modified in the following ways: - A new pane named "Design Units" has been added to the profile window. It aggregrates results on a per design unit basis. - "sum(Mem in)" and "sum(Mem in(%))" columns have been added to the Ranked and Design Units profile panes. These columns report cumulative values for memory in and memory in %, providing another metric to use when examining memory profile results. - Memory values are displayed in the profile windows as comma separated numbers rather than with K and M suffixes. This provides correspondence between the printed size of the number and its actual value; the goal is to make the data easier to read. * When encrypting Verilog source text any macros without parameters defined on the command line are substituted (not expanded) into the encrypted Verilog file. ______________________________________________________________________ New Features Added to 6.3g_p1 * The bp command (file/line breakpoints) now accepts an optional label -label. This label can be used with the bd (breakpoint delete), enablebp (enable breakpoint point), and disablebp (disable break point) commands. If a new breakpoint is created using a label already in use by an existing breakpoint, the older breakpoint is deleted. Labels used in both file and signal breakpoints must be unique. In other words, a file breakpoint cannot use the same label as a signal breakpoint. * Added buttons for rising/falling edge transition in Wave window.