Release Notes For ModelSim Altera 6.4a Aug 28 2008 Copyright 1991-2008 Mentor Graphics Corporation All rights reserved. This document contains information that is proprietary to Mentor Graphics Corporation. The original recipient of this document may duplicate this document in whole or in part for internal business purposes only, provided that this entire notice appears in all copies. In duplicating any part of this document the recipient agrees to make every reasonable effort to prevent the unauthorized use and distribution of the proprietary information. TRADEMARKS: The trademarks, logos and service marks ("Marks") used herein are the property of Mentor Graphics Corporation or other third parties. No one is permitted to use these Marks without the prior written consent of Mentor Graphics or the respective third-party owner. The use herein of a third-party Mark is not an attempt to indicate Mentor Graphics as a source of a product, but is intended to indicate a product from, or associated with, a particular third party. The following are trademarks of of Mentor Graphics Corporation: Questa, ModelSim, JobSpy, and Signal Spy. A current list of Mentor Graphics trademarks may be viewed at www.mentor.com/terms_conditions/trademarks.cfm. End-User License Agreement: You can print a copy of the End-User License Agreement from: www.mentor.com/terms_conditions/enduser.cfm. ______________________________________________________________________ Product Installation and Licensing Information For brief instructions about product installation please visit the "install_notes" file in www.model.com. The install_notes file can be viewed at: [1]http://www.model.com/products/release.asp For detailed information about product installation and licensing see the ModelSim Start Here Guide. The manual can be downloaded from: [2]http://www.model.com/support/documentation.asp Release Notes Archives For release notes of previous versions visit the release notes archive at: [3]http://www.model.com/support/default.asp or find them in the installed modeltech tree in /docs/rlsnotes How to get Support ModelSim Altera is supported by Altera Corporation * World-Wide-Web Support [4]http://www.altera.com/mySupport ______________________________________________________________________ Index to Release Notes [5]Key Information [6]User Interface Defects Repaired in 6.4a [7]Verilog Defects Repaired in 6.4a [8]PLI Defects Repaired in 6.4a [9]VHDL Defects Repaired in 6.4a [10]FLI Defects Repaired in 6.4a [11]VITAL Defects Repaired in 6.4a [12]SystemC Defects Repaired in 6.4a [13]Assertion Defects Repaired in 6.4a [14]Mixed Language Defects Repaired in 6.4a [15]Coverage Defects Repaired in 6.4a [16]General Defects Repaired in 6.4a [17]Mentor Graphics DRs Repaired in 6.4a [18]Known Defects in 6.4a [19]Product Changes to 6.4a [20]New Features Added to 6.4a ______________________________________________________________________ Key Information * The following lists the supported platforms: + win32aloem - Windows 2000, XP + sunos5aloem - Solaris 8, 9, 10 + linuxaloem - RedHat 7.2 and higher. ______________________________________________________________________ User Interface Defects Repaired in 6.4a * From the Wave window the user gets the following message after reaching the maximum time (9223372036854775807) then Zooming out: wlfReadDataOverRange: time range is negative or null. * Dataflow operations using certain mixed-language designs could cause vsim to crash. * Could not expand packed SystemVerilog 3-dimensional arrays in the Wave Window. * The project properties dialog, within the Project window, produced an error if a .sv (SystemVerilog) file was selected. Once this error occured, the dialog would no longer raise, even if a non-SystemVerilog file was selected. The project properties dialog now functions properly for all file types, includign .sv files. * The location that the registered icons for .wlf, .v, .vhd and .mpf files has changed. The icons were stored in an executable that is no longer shipped with all Windows versions (OEM/Education). The icon resource has been moved to vish.exe, which is included in all Windows based releases. * Under some conditions logged Verilog cell internal signals would not get relogged following a simulator restart. * Arrow keys now cause scrolling for the Classgraph, Dataflow, FSM and Watch windows: + Arrow key with no modifier causes scroll by small amount. + Control+arrow key causes larger scroll amount. + Shift+arrow key causes display to be shifted to edge of display. * It was possible for the Source window annotation data to become "out of sync" with the compiled data when the source code was edited and saved and then a restart was done after recompiling. * Set Root, Ascend Root and Reset Root popup menu picks did not work in Design Units tab of Profile window. Profile report dialog did not support Design Units report type. * "do" files that make external calls could generate a "command not found" error. Issuing a shell command such as "ls" or "rm" would not evaluate properly. This issue has been fixed. Adding a preceding "eval", such as "eval ls" or "eval rm" would not produce the error. * By instance code coverage for generate blocks was not supported properly. Generate block coverage (both VHDL and Verilog) now displays properly in the Instance Coverage window as well as a Source window that is configured to display by instance coverage. * When using the "contains" filter and entering a filter pattern that resulted in no matches, clicking on a column header for the active window (i.e. to set the sort column) would result in a crash. * Loading a merged UCDB with -viewcov caused Tcl errors after repeated tests. This only happened on Windows. * Using the key sequence Shift-Insert would result in a duplicate paste. * Some problems with displaying instance exclusions in the Current Exclusions window have been fixed. * Current exclusion panel and missed coverage panel in viewcov mode did not exclude the line containing case statement if the line after it is excluded by scope. ______________________________________________________________________ Verilog Defects Repaired in 6.4a * The +initreg and +initmem options applied to vlog caused vopt to run significantly slower. * In some cases, optimizations would incorrectly apply forces when nets were connected via interface ports. * In some complex assignments to multibit registers where distinct processes were sensitive to different bits of the reg, it was possible that a fatal error could be encountered during simulation. * The vlog compiler crashed if a time literal (e.g. "1ns") was used as a default task or function argument value and the task or function was declared in a package or $unit scope without a specified time precision. * On a Queue of virtual interfaces, trying to do a push_back would result in an error like: 'const ref' can't be passed in function push_back * Using bind inside a generate block would error out in vopt with an incorrect error message saying: 'invalid bind target' and, get silently ignored in novopt mode. * Conditional operator when used to return a value in a function of a class would sometimes give error such as: ** Error: types are not assignment compatible. * vlog will crash when one of the built-in SystemVerilog functions (e.g. $size, $left, $increment, etc.) is called without any arguments. This is now fixed and will report an error. * An error for the following illegal foreach construct might have not been reported. foreach (arr[i][3:1]) ... * Under certain conditions, a gate-level optimized cell selected the delay from a shorter ifnone module path rather than an explicit module path. * In some cases an Unexpected signal: 11 occurred in vopt when the following assignment was used: c.a = ( b = 1); * Under certain circumstances, $period and $width checks would be simulated with their default limit values and not values from SDF. The write timing command showed the SDF limits, but violation messages showed the default limit. * When multiple processes were blocked doing a semaphore::get() call on the same semaphore and then a semaphore::put() call was made with more than 1 key the get() calls would wake up in the wrong order. * When multiple break statements were used within a group of nested begin..end blocks, the blocks would sometimes exit as if a break occured even when it was not executed. * A function that returns a conditional expression such as: function automatic int foo(int a); return (choose ? 10 : 20); endfunction might have given an internal error such as: Internal error: ../../../src/vlog/vallocate.c(1399) self * Fixed internal error in vopt that produced the following error message: ** Error: test.v(3713): Internal error: ../../../src/vlog/vgendecl.c(10453) clk != NULL * A fatal error of the form "Fatal: Trouble with Simulation Kernel" could result if a parameterized class defined a "self_type" and then referred to a parameter or type it was defining by way of a "self_type::" reference. * If a parameterized class was defined with a type parameter whose default was a nested specialization, fatal errors could occur during elaboration. The form of such defaults would be similar to the following: class C #(type T = B #( A #(5) ) ) * If a hierarchical reference was made from a parameterized class or a class inheriting from a parameterized class to some other module, an optimized simulation could fail to elaborate with an unresolved reference error. * In some cases, most easily exposed in parameterized class contexts, using a foreach with a queue could result in elaboration errors saying that an index's "size" could not be resolved. * Sorting a large array (more than 1000 entries) using a 'with' clause sometimes produced the wrong result, either incorrectly sorted, or with entirely different entries. * Verilog gate-level optimizations could cause false timing check violations to be reported. * $sscanf would cause simulation crashes when the buffer was an input net. * rand_mode and randc status information are now copied when a dynamic array is resized with an initialization expression (eg. x = new[5](x);). This is now similar to the shallow copy for a class. This is also now the behavior when a dynamic array is resized by randomize, the rand_mode/randc status of existing elements are retained. * Casting like mytype'{16'b0} might result in a crash in vlog or vopt. * While trying to access a class member from within a streaming concat along with the 'with expression might result in an Internal Error like: Internal error: ../../../src/vlog/vgenexpr.c(7643) typeof(decl) == USER_INSTANCE * Extern tasks & functions that used "::" in the argument defintions would sometimes incorrectly report an error indicating the extern declaration and the actual declaration did not match. * Assignment of real or shortreal types to an element of an array of packed values performed an incorrect conversion from the real value to the packed type. * Multiply nested macros would fail to expand. Vlog produced the error "Cycle detected or recursion limit reached during expansion of macro...". * vlog sometimes crashed when compiling files with timeunit resolutions. * An event control containing a cross-module hierarchical reference to a clocking block variable triggered inappropriately. * Using 'foreach' over an associative array of class type index might have given an error like Error: (vsim-3043) test.sv(17): Unresolved reference to 'I'. This has now been fixed. * Vlog would hang when a block comment containing pragmas did not have white space immediately after the closing text: "*/". * Task calls were incorrectly optimized away in the case that the task input/inout formal was not referenced in the task body but was referenced externally via a hierarchical reference. * In some cases involving SystemVerilog pacakges, the following internal error was reported: ** Error: test.sv(6): Internal error: ../../../src/vlog/vgencode.c(78) storage_levelOf(loc) > 0 * Ill-formed cross might have an empty user-specified bin. This was incorrectly triggering a fatal error. A warning is issued and covergroup construction will continue in such cases. * Period timing check violation messages could contain incorrect event times. * When distributed (internal) delays were longer than the retain delay, for a specify path, the event scheduling was incorrect. This caused incorrect/missed signal transitions. * Non-protected design units following a protected region read with vlog could cause design corruption. * vlog exited with "Unexpected signal: 11" while compiling Verilog files on PE only. * Gate-level optimized cells with 2 tristate outputs could select the wrong iopath delay. * If an incorrectly named by-name port association was made with an interface port, vopt would issue an incorrect error similar to the following: ** Error: test.sv(19): For instance 'c', interface port 'b' requires an instance of interface 'intfB', but was passed a 'intfA'. The vopt analysis has been corrected to indicate that the real error is related to an incorrectly named port in the port association. ______________________________________________________________________ PLI Defects Repaired in 6.4a * The PLI was returning internal scope objects named #vsim_capacity# and of unrecognized fulltype 1621 from some iterations. This has been fixed so that these objects are no longer visible to the PLI. * There have been some changes to the VPI view of string variables presented to VPI applications. The IEEE standards committee recently clarified that the size of a string variable should be measured in characters, not bits. The tool previously reported string variable sizes in units of bits. Some bugs in the VPI access to string vars that are members of arrays have also been fixed. * A vpiEnumConst passed as a VPI systf argument was not handled correctly by the VPI. * VPI requests for the value of a packed structure using vpi_get_value() would return incorrect data (zeroes) in all bits above the bottom 32, if the value request format was vpiVectorVal. This has been fixed. * Class object members when passed as systf arguments inside the class task was crashing when tried to access their value. * VPI was not giving the correct type information for packed enum variable and for the members of array of enum variable. * When iterating for vpiTypespecMember on Structs/Union, the name for the typespec member was not coming correctly. * The vpiRange iteration for vpiNamedEventArray was not implemented. This has now been implemented. * The vpiNamedEventArray iteration was not implemented for Module, Task, Function, NamedBegin and NamedFork. This has now been implemented. * A bug affecting the behavior of vpi_put_value on certain object selections when vpiInertialDelay or vpiTransportDelay was specified has been fixed. The effect of the bug was to inhibit matching of pre-existing events that the LRM requires to be canceled for these flags, thus causing them not to be canceled. * The vpiVector and vpiScalar properties returned from vpi_get() were incorrect for nets with multiple packed dimensions. This has been fixed. * VPI systf arguments that were indexed selections within unpacked arrays of reg were always typed as vpiReg. In fact, such objects can have vpiRegBit or vpiRegArray VPI types, depending on the precise indexing. This change will result in some objects having different VPI types. It may also result in duplicate argument evaluations, as evaluation is necessary when the indexing is investigated. ______________________________________________________________________ VHDL Defects Repaired in 6.4a * VHDL simulation could given an elaboration time error and then crash. This would occur if the error was in an instance that was instantiated under a generate loop. * If multiple logical libraries are mapped to the same physical library and a configuration configures a design unit in that physical library, an optimized design may have crashed when loaded or during runtime. This occurred when the design unit could be referenced via multiple logical library names and the optimization information was only found via one of those library names. * The drivers command ignored ports connected to resolved composite signals. The command now reports the connection information. * A VHDL generate statement with a negative value in the range of indexes could crash during design elaboration. * An entity port's whose width is controlled by a generic could incorrectly report a width mismatch if the generic is set within a VHDL configuration. * Record signals that contained fields that are resolved records caused the simulator to crash when elaborating the design. * Component ports with types determined by generics would give an internal error. * Port maps of block statements would fail with slices from a multidimensional array in the actual. * The vcd add command could crash the simulator when connected vector ports were added to the VCD file. * Compiling a package with the same name as one of the Vital packages into a library with the same name as the library where the genuine Vital package is installed, and then using that package in a design could sometimes result in a crash when loading the design. * A std_logic_vector of length 1 inside a record would cause a crash when the record types was used for a package signal. * A crash would occur if a actual to a vector port is a constant, the size of the port depends on the range of a generic, the generic is unconstrained, the generic is initialized with an aggregate, and the generic is left open. * Aliases of subprograms were not always being treated as overloadable. * vsim would crash when logging signals after a checkpoint and restore. * If the architecture and its corresponding configuration declaration have configuration specification and component configuration respectively and the architecture body had a generate loop, then vsim might crash or hang in some cases. This has been fixed. ______________________________________________________________________ FLI Defects Repaired in 6.4a * Creation of a FLI driver on a resolved composite signal would cause the resolved composite signal to stop being evaluated. ______________________________________________________________________ VITAL Defects Repaired in 6.4a ______________________________________________________________________ SystemC Defects Repaired in 6.4a * Creating global time based objects like sc_time or sc_clock would lead to error in setting time resolution. This will not lead to an error as long as the default time resolution of "1 ns" is used. * The step commands now takes an additional argument "n" where "n" is a positive integer. The following commands are now supported. step step -over run -step run -over * Added partial support for the parameterized value usage in DPI-SC task/function formal type. The following cases remain unsupported: 1. if parameterized value is used in field type of struct or union. 2. if parameterized value is used for SystemC datatypes. All parameterized type usage remain unsupported in DPI-SC. * Segmentation fault while creating SystemC module variables is now fixed. ______________________________________________________________________ Assertion Defects Repaired in 6.4a * Corrected a problem with assertion attempt count reporting where a lower level always operator could sometimes cause the reported attempt count to mirror the clock count, where it should have shown just 1 attempt. ______________________________________________________________________ Mixed Language Defects Repaired in 6.4a * Incorrect values would sometimes get assigned to VHDL generics of type unconstrained arrays, when they get overriden from SystemVerilog (in a SystemVerilog instantiating VHDL scenario). * vopt would sometimes give an incorrect errors for bind-to-VHDL calls with formals of SystemVerilog user-defined types on the Windows platform. * vsim invoked with a VHDL configuration would sometimes give errors when binding to VHDL using the SystemVerilog bind construct. * Binding to a VHDL instance (using SystemVerilog bind construct) was broken in incremental mode, when the target VHDL instance was under a Verilog hierarchy. * Optimized Verilog gate-level full timing cells, with timing checks, may not evaluate correctly under a VHDL netlist. ______________________________________________________________________ Coverage Defects Repaired in 6.4a * Excluding expression rows did not update Missed Coverage and Details windows in live simulation mode. * Excluded FSMs showed up in report and Missed Coverage window. * The Missed Coverage window displayed excluded FSM states and transitions in live simulation mode. * Fixed a problem in which VHDL generate blocks in vopt would not show code coverage data. * Fixed a problem in which a crash would occur if a VHDL architecture was compiled with code coverage on, and the configuration was compiled without code coverage on. * Having the VHDL clocked flip/flop "clkOpt" optimization enabled when code coverage is on has caused confusion among users. With this optimization, processes that implement an edge-triggered register with reset are optimized so that the processes are invoked only on the correct edge of the clock, or reset. This causes branch coverage to record zero counts for the other edge of the clock, which has caused confusion. Consequently, we now disable the clkOpt optimization when CoverOpt is less than 4 (the default is 3). Turning off this optimization does slow down simulation. If you still want clkOpt enabled, use CoverOpt = 4. * A performance problem has been fixed with code coverage when there are large numbers of toggles. * A problem has been fixed in which generate blocks would not show code coverage after restart, when in novopt mode. * When VHDL with VITAL cells is compiled in vopt flow with FSM coverage turned on, vsim sometimes crashes during elaboration with following error: ** Fatal: Internal error: ../../../src/vsim/cover.c (4070) * Code coverage is now giving results for SystemVerilog nested modules, interfaces and program blocks. One remaining issue is that if a nested module has more than one instance, only one of the instances will show code coverage data, and the data therein will be the sum of all the instances of that module. This will be improved in a later release. * In UCDB files, code coverage scopes corresponding to branches, conditions, and expressions were given a dummy name of "dummy_coverage_scope". Now, the scope is named branch#line# (for branches), cond#line# (for conditions), or expr#line# (for expressions), with "line" being the line number from the source file containing the coverage item. * This fix contains 2 items: 1. Saving Current Exclusions report used to generate one exclusion command per line which might be very long, now command lines longer than 80 characters are split on multiple lines. 2. In Tools main menu, underneath Coverage Report menu has 3 menu items. The menu item called "Exclusion..." is now "Exclusions...". * Fixed a problem in which code coverage could crash when the user has a local copy of a VHDL package that has the same name as an MTI-supplied package. * HTML coverage report used to display "0" for assertion coverage bins that did not exist (due to being optimized out). It now displays "-" for these non-existent bins. * Exclusion had no effect on nested branches in Missed Coverage window in viewcov mode. * vcover crashed while reading corrupted UCDB files. Now it exits with an error message. * Fixed incorrect XML report format for FEC expressions and conditions. * The Comment column in the Covergroups tab in the Analysis pane is now visible by default. * The XML Testplan Import utility had some issues with linking testplan sections to a specific instance of a covergroup (or its contents) if the instance name was an escaped identifier. To handle this, the import process now checks for instance names which start with, but do not end with, a backslash. In this case, a space is added to the identifier when it is saved to the tag command. So the proper way to specify a single instance of a covergroup would be one of the following: 1. covergroup,\/cvg/instance/name; 2. covergroup,\/cvg/instance/name:coverpoint; * Fixed 'coverage exclude -scope ' error when contains dataset name. * Expressions would sometimes evaluate to incorrect output with short-circuiting enabled with code coverage on. * Design units in bydu coverage report are now printed in alphabetical order of design unit names. * The error message saying "Error in UCDB reader reading UCDB_DU_PACKAGE" was printed while loading a merged testplan UCDB file in viewcov mode. * Fixed a case statement exclusion problem, now when a case statement is excluded all its bins are excluded too. Before, excluding the line containing the case statement caused some bins to not be excluded. * Simulation run setting the context to a process followed by selecting a coverage dataset would cause a Tcl error. This has been fixed. * The -covershort and -nocovershort options were not recognised by vcom and vlog in the PE version of ModelSim. * Enabling of toggle coverage in an optimized design resulted in false "part-select out of bounds" error messages from vopt in some cases. ______________________________________________________________________ General Defects Repaired in 6.4a * When -gen_xml was used with vcom or vlog, the _info file could be modified. * vcd2wlf in rare cases would swap the weak WeL and WeH values in the resulting WLF file. * Occasionally the simulator would hang or crash when File->Quit is selected from the menus when the simulation is actively running. * vmake would crash in certain situations. * vcd2wlf would sometimes incorrectly handle spaces within the brackets of bus element declarations. * Using the -nocase switch to vcd2wlf sometimes caused a problem with the case of port values. * A file that is opened in VHDL for read access during a "checkpoint", that does not exist when a "restore" is done, will now not result in error unless the file is actually attempted to be read. * The performance profiler crashed the simulator, producing the error message "Internal error! Stack trace within handle_tick". This occurred when QuickThreads were used by PLI/VPI/FLI/DPI applications. * If an optimized design "black-box" was referenced by design elements that were not compiled with vopt, occasionally elaboration errors could result. The error might typically look like: could not find machine code for ... . * The command power report -bsaif did not correctly handle escaped identifier names with a pathname delimiter in them. ______________________________________________________________________ Mentor Graphics DRs Repaired in 6.4a * dts0100308219 - Dataflow window doesn't support scrolling window by arrow keys. * dts0100470209 - Cannot resolve path to VHDL generate with negative range. * dts0100476901 - Cannot step multiple lines in C Debug. * dts0100477642 - vsim crash during load when Vital libraries are compiled locally. * dts0100483348 - Zoom error in Wave window. * dts0100483402 - SDF annotate simulation do not specified the delay on vopt mode. * dts0100487304 - evcd dump can not log weak 1 signal which pass through tranif1(). * dts0100494357 - vsim 6.3f returns the wrong character count for a line of text in VHDL. * dts0100495374 - Request to create HTML coverage report that has a page which looks identical to original XML testplan with coverage populated. * dts0100500341 - Semaphore get() method does not respect FIFO order. * dts0100500120 - SV, can't expand data for a 3-D packed array in the wave window. * dts0100502719 - SV bind Error with Unbased_unsized literal. * dts0100498488 - Support conditional binding. * dts0100505186 - +initreg/+acc option applied to vlog makes vopt take a long time. * dts0100505210 - Array slices not updating correctly w/o -noRestoreAtomics. * dts0100505815 - Not all waveform signals are displayed. * dts0100506009 - vlog segfaults when trying to compile the SV code. * dts0100506519 - Loading a merged UCDB with -viewcov causes tcl errors after repeated tests. * dts0100506859 - Constraint solver fails to find a relatively simple solution. * dts0100507063 - Always block on posedge clk also executing for negedge. * dts0100507110 - Internal error with -coverage from image package. * dts0100507955 - Simulator is not shipping the completed TLM 2.0 library. * dts0100508463 - External programs run from a dofile are not found. * dts0100508522 - Correction to Simulator's 6.4 User Manual section "Binding to VHDL Enumerated Types" * dts0100508611 - SIGSEGV with option -coverage. * dts0100508837 - 6.4 simulator crashes with "** Fatal: Trouble with Simulation Kernel." message. * dts0100508871 - Coverage merge segmentation violation. * dts0100509506 - 6.4 Fatal unexpected signal error during vsim. * dts0100509750 - Wrong paths in mspa_vopt.v when using -pa_prefix/-pa_replacetop option. * dts0100510022 - Option -nocollapse produce a wrong simulation. * dts0100510260 - Problem with $sscanf parsing of strings. * dts0100510282 - Error: "Bad pointer/access type passed to memory" when resizing dynamic random arrays in post_radomize() function. * dts0100510927 - Port size (8) does not match actual size (32)--fails during vsim elaboration in 6.4. * dts0100505992 - Simulator returns a fatal error when global time objects are used in the SystemC code. * dts0100510941 - Internal error during vsim due to templated super class parameters and the unpacking operator. * dts0100510950 - Coverage exclusion not taking effect in Source and Missed Coverage window. * dts0100510951 - A problem while removing name of the coverage file from the instance path. * dts0100511003 - Coverage merge problem -6820 error should happen but is not. * dts0100511495 - Mismatched `else directive not reported. * dts0100511559 - vmake segfaults in 6.4 version. * dts0100511577 - Record signals that contained fields that are resolved records caused the simulator to crash when elaborating the design. * dts0100504670 - File->Quit action should check for running sim and break then quit. * dts0100506558 - "-gen_xml" should not update the _info in the library. * dts0100512020 - GUI crash in 6.4 when clicking on the Instance tab in the workspace window after entering any text that returns nothing in the Contains bar. * dts0100512109 - UDP coverage short-circuiting fails. * dts0100512184 - Wrong hold violation with +acc=bmprn. * dts0100512188 - Component ports with types determined by generics would give an internal error. * dts0100512278 - Add the ability to suppress the message: ** Warning: xxx.v(36): Connection width does not match with of port "". * dts0100512536 - vlog sometimes crashed when compiling files with timeunit resolutions. * dts0100512724 - Missing equals sign between attribute and attribute value. Error processing resource C:\Documents and Settings\psukhija\Desktop\Xml_report_error\Xml_report\test_6.4.xml. * dts0100512739 - "-novopt" results in wrong ** Error: (vsim-3033) top.sv(22): Instantiation of 'irq_gen_chk' failed. * dts0100512867 - Unresolved reference with foreach. * dts0100512898 - Error tkerror {couldn't open "/tmp/tmp.html" : permission denied} when trying to open online documentation. * dts0100513164 - rand_mode bits should be copied when a constraint resizes. * dts0100513186 - Enabling condition coverage gives different simulation results. * dts0100513292 - vcover rank command's runtime needs improvements. * dts0100513690 - Issue with direct configuration when it is passed to the vsim command for bind. * dts0100515505 - The vcd add command could crash the simulator when connected vector ports were added to the VCD file. * dts0100515766 - Multiply nested macros would fail to expand. vlog produced the error "Cycle detected or recursion limit reached during expansion of macro...". * dts0100515776 - SHIFT + INSERT, the "cut" line is inserted twice. * dts0100449506 - Results differ between optimized and unoptimized simulation with VHDL instantiating Verilog. * dts0100516653 - Compiler crash with covergroups. * dts0100516986 - Incorrect simulation results when distributed delays are longer than retain delays. * dts0100514999 - Issue with backward compatible SAIF format with extended identifiers. * dts0100515458 - Internal error by vlog/vopt when generating machine code. ______________________________________________________________________ Known Defects in 6.4a * On Windows platform, If Destructor breakpoint on SystemC object is set via command "bp -c < function_name >", Debugger sometimes does not stop at the breakpoint. * On Windows platform, if breakpoint is set on a SystemC object destructor, Debugger sometimes crashes while quitting simulation. This crash can be avoided by setting env variable SC_NO_LIB_UNLOAD, which will prevent unloading of the shared library. * Syntax highlighting may not function properly in the Source window (all the source is shown as plain text). You can fix this problem by editing ~/hte/v2_38/hte.ini (where ~ represents your "HOME" directory) and deleting the line that says: languages=cxx tcl verilog vhdl XML PSL * The viewcov mode version of "coverage clear" has a known difference in behavior compared to the vsim mode version. In the viewcov mode version, clearing coverage data in a design unit instance does not affect the coverage data for that design unit, itself. Also, if you clear coverage data in a design unit, all instances of that design unit are not affected by that operation. In vsim mode, the data is more tightly linked such that one operation affects the other. In viewcov mode, if you want to have correct data correlation between instances and design units, then you need to clear both instances and design units. * The simulator will hang if it tries to create a WLF file while running on a Linux 64-bit operating system from a working directory which does not support large files. One common instance of this is executing an add wave command, when the working directory was created under an older 32-bit Linux OS. This is a Linux operating system bug and cannot be fixed by the simulator. A workaround for release 6.3 and above is to execute the simulator with command line option -wlfnolock. * The stack unwinder on the linux_x86_64 OS is unreliable. The unwinder is the fundamental facility provided by the OS for sampling where program execution is at. The unwinder is necessary for gathering performance data. This is a known issue with this specific OS and is why performance data will be incorrect or non-existent on this platform. * Users should be mindful of enabling both performance profiling and memory profiling at the same time. Memory profiling requires much overhead process, and it can skew the results of the performance profiling data. * On certain (RedHat) Linux Operating System versions the "-restore" feature occasionally fails. This is due to the memory allocation security (anti-hacking) feature of Linux. RedHat Enterprise release v.3 update3 was the first version to have this security feature. In these Linux releases two consecutive program invocations do not get the same memory allocation foot-print. For the "-restore" feature the simulator relies on having the same memory allocation foot-print. Users are advised to re-try this feature a few times as on average 3 out of 5 attempts are successful. In recent Linux versions, an override for this anti-hacking feature is provided. Please use it at your own discretion. * In code coverage, there is no way to exclude a condition or expression table row for the case of more than one table on a line and the table in question is not the first table on the line. * Support of debugging C code during a quit command was disabled on Windows. The corresponding C Debug command cdbg stop_on_quit was also disabled on Windows. * Specparams can be learned during the learn flow, but cannot be found on consumption. The workaround is to use full +acc deoptimization. * Concatenations and bit slices are not yet supported for System Verilog clocking blocks. * On Red Hat Enterprise Linux release 5 platform, If SIGSEGV signal occurs during the simulation and if CDEBUG is on, C-debugger traps the signal, and when continued, vsim gets terminated right away, instead of exiting with proper error status. * vlog will now print an "unsupported" error message for nested design-units, as this feature is not fully supported in 6.3. This error may be suppressed using the -suppress 2230 command-line options. * For viewing events in Expanded Time in the List window, use the "configure list" command with the "-delta events" option. "events" is added to the "all", "collapse", and "none" options for the "-delta" argument. These options control the details shown in the List window and in writing list files. This was documented incorrectly in the "Expanded Time Viewing in the List Window" section of the "Waveform Analysis" chapter of the User's Manual. The "write list -events" command serves a different purpose (which has not changed) and is NOT used to control Expanded Time viewing in List window. * The "examine", "searchlog", and "seetime" commands have NOT been enhanced for use with Expanded Time. This was documented incorrectly in the "Expanded Time Viewing with examine and Other Commands" section of the "Waveform Analysis" chapter of the User's Manual. * If you have code coverage on in VHDL and get the following sort of warning: # Loading mypackage(body) # Internal Warning in process_sub: failed to find local inlined subprogram called in pkg # (mypackage ); flags 7 filenum 0 lineno 241 tokno 2 # Disabling code coverage for this inlined subprogram Then add the -noFunctionInline option to vcom for that package, or reorder the subprograms in the package body to be defined before they are used. * Code coverage is now giving results for SystemVerilog nested modules, interfaces and program blocks. One remaining issue is that if a nested module has more than one instance, only one of the instances will show code coverage data, and the data therein will be the sum of all the instances of that module. This will be improved in a later release. ______________________________________________________________________ Product Changes to 6.4a * The priority of +initreg/+initmem options is adjusted from the previous versions. Now, the +initreg/+initmem options specified to vopt with design unit or instance name have the highest priority. After that, these options applied to vlog have the next priority and the vopt +initreg/+initmem options have the last priority. In earlier versions, the +initreg/+initmem options specified to vlog command had higher priority than design unit or instance specific +initreg/+initmem vopt options. * To improve usability, the Run toolbar has been changed: a Break button has been added. * The text-based windows (Transcript, Notepad and Source) now have an "inline" search bar (instead of a dialog box) which supports incremental searching. The previous behavior can be restored using the "Main/InlineTextSearch" option. * Several fatal elaboration errors will now print the line # where the error occurred. * The new enhanced support of analog format within the Wave window includes a change to the output created by "write format wave". In pre-6.4 the output for the "add wave" commands would include "-offset" and "-scale". Starting in 6.4 the output will instead use "-min" and "-max". * When vpi_iterate and vpi_scan are used on an array of instances, the individual elements will now be returned left-to-right, where they formerly were returned low-to-high. For example if they are applied to "mymodule u1[2:0]();", the elements returned will be u1[2], u1[1], u1[0]. * Each tag in a taglist (used as data extraction parameters) may now include a subset of the XPath syntax to identify elements not only by tag name but also by the contents of attributes attached to said elements. This pseudo-Xpath syntax only handles "=" and "!=" and can only examine the attribute values attached to the element being compared. Moreover, only one attribute comparison may be performed. For example, the following extraction parameter: "-starttags Worksheet[@ss:Name=Sheet1]" will match the following element in the incoming XML: ... but will not match the following element: ... * The behavior of several extraction parameters in the XML Import utility has been clarified to allow various parameters to work more independently. The affected parameters are: starttags, stoptags, excludetags, and startstoring. * VCD extensions for SystemVerilog supported as per Section 24: VCD Data in IEEE-P1800. LRM is not extending VCD for interfaces and programs. They will be dumped as "module" scope. * The source window has been changed to remove the separate column used to display breakpoints. Breakpoints will be shown within the "line number" column (as they were in the pre-6.3 releases). The LMB event handling has been improved to avoid inadvertant setting of breakpoints. Also, there is now a subtle visual separator bar between the text area and the line number column to help guide the user during text selection. * The coverage numbers shown in the source window can appear to be in conflict with what's shown in the "Missed Coverage" window. This occurs when the Missed Coverage window is in "By Instance" mode and the source window is in "By File" mode. The latter is the default for the source window but it gives no indication what its current mode is. To make it clear for the user, the title bar of the source window will be enhanced to include the current coverage data mode(either "by file" or "by instance"). * The Contains toolbar now supports multiple wildcard modes. The default mode is now "glob" style which is the more common form of wildcards as found in UNIX shells. The wildcards are *, ?, [chars], and \x where x is any character, removing that character's special meaning. Previously, this filtering tool used full regular expressions. This option is selectable from the menu button in the Contains entry box, by selecting the value "regular-expression". The third option, "exact", does not use wildcards so no characters have any special meaning. In all modes, the search patterns are considered case insensitive. If a case sensitive pattern is needed, use the regular-expression mode and perpend the search string with "(?c)". The preference variable PrefMain(ContainsMode) defines the filter mode for all windows with one of the values of "glob", "regexp", or "exact". More information on regular expressions can be found in the Tcl reference manual under "re_syntax". Information on glob style matching can be found in the Tcl reference manual under the "string match" command. * Macro arguments to Verilog and SystemVerilog macros are now expanded prior to substitution into the macro body. * SDF annotation of RECREM or SETUPHOLD matching only a single setup/hold/recovery/removal timing check will result in a warning message. * The transaction recording engine no longer issues a warning if a design attempts to record a transaction of zero length. * The log and nolog commands are now supported for transaction streams of all kinds. TR streams created through the SCV or Verilog APIs have logging enabled by default. The rule is that a transaction will be logged in WLF if logging is enabled at the simulation time when the design calls ::begin_transaction() or $begin_transaction. The effective start time of the transaction (the time passed by the design as a parameter to beginning the transaction) does not matter. Thus, a stream could have logging disabled between T1 and T2 and still record a transaction in that period using retroactive logging after time T2. A transaction is always entirely logged or entirely ignored. * PSL LTL and OBE operators are now disabled by default. Use -pslext vcom/vlog/vopt switch to enable these operators. * The Win32/Win32PE platform executables (excluding vish.exe) are now linked with the /LARGEADDRESSAWARE switch. This switch allows an executable to allocate an extra gigabyte of process space (up to 3GB). The additional gigabyte of process space is available on Windows configurations that include the /3GB (/userva on Vista) boot switch. Vish.exe is not linked with /LARGEADDRESSAWARE and we do not recommended that this switch be used with vish.exe. Testing vish.exe with this switch exhibited a tendency to exceed the one GB system limitation which results in a crash. When the simulator's GUI displays several windows with large amounts of graphical data and a full redraw occurs, a temporary surge in the allocation of system memory can cause the limit to be exceeded. * The behavior of virtual expressions has changed in a subtle way. Normally when a virtual expression contains a relative context pathname, for example u1/x2/b, the current context would be used in order to resolve the name. However, relative paths that started with a toplevel name would also be recognized, ignoring the current context. This unintended behavior has been corrected so that the current context is always used to resolve a relative name. This may cause some previously accepted virtual expressions to fail to be accepted. * modules found through source library search are no longer treated by default as if they contained a `celldefine compiler directive. To obtain the old behavior, add +libcell to the vlog command line. Source library search is enabled with -v and -y compilation options. Whether a module is considered a cell or not affects logging defaults with log -r *, coverage defaults within the module, and PLI access routines acc_next_cell and acc_next_cell_load. This change simplifies migration from other simulator products. * Support for Verilog hierarchical references through VHDL design units has been greatly improved. It is now possible for hierarchical references from a higher level Verilog to refer to objects in a Verilog module instantiated beneath a VHDL design unit. In previous releases, upward references from a lower level Verilog module would only work if the target's scope was a direct parent, or a silbing that was instantiate lexially earlier in source. This restrictions are now removed. Hierarchical references that pass through a VHDL design will not work in the follow cases: + Is the target of a defparam. + Used as an actual to a unconstrained VHDL port. + Target of the reference is a VHDL object. * A new toolbar has been added to the Wave window for access to the existing Bookmark functionality. * Enabled use of the "contains" filter for the Files tab of the Workspace window. * Support for some additional VPI features has been added in this release. The vpiDriver transition has been extended, and partial support for vpiContAssign objects has been added. * When encrypting Verilog source text any macros without parameters defined on the command line are substituted (not expanded) into the encrypted Verilog file. * Wave searches initiated from the keyboard or toolbar buttons can now be stopped by clicking the Wave window's "Stop Wave Drawing" toolbar button or the Simulation toolbar's "Break" button. * The SystemVerilog array manipulation methods now reflect the latest changes in the P1800 Draft5 version of the LRM, in that iteration occurs only in the top dimension of the array. That is, the correct way to sum the elements of a 2-dimensional memory, as indicated in the LRM's example, is: logic [7:0] m [2][2] = '{ '{5, 10}, '{15, 20} }; int y; y = m.sum with (item.sum with (item)); // y becomes 50 => 5+10+15+20 Previously, ModelSim iterated through all the unpacked dimensions, "[2][2]" in this case. * When using C-debugger to debug quit callback functions, user needed to turn on 'stop on quit' mode. User start debugging by issuing 'quit -f' command. When simulation ends, user needed to quit C-debugger using 'cdbg quit' and then GUI using 'quit -f'. Now, Users do not need to issue extra commands at the end of the run. Simulator automatically quits C-debugger and GUI, after debugging is done and simulation has stopped running. * If a VHDL signal is read during elaboration the value read may differ from value read in previous releases. The VHDL LRM considers this illegal(Section 12.3) but tool behavior has always been to just warn and allow a value to be read. What the value read has always been undefined. Additionally previous releases allowed functions and procedure with signal parameter to be called during elaboration. This is now illegal and reported at compile time. * The menus which control the functional coverage tab display options (assertion, cover directives and functional coverage) have changed slightly. Most significant of the changes is that each pane now has a separate control for "Show All Contexts" and "Recursive Mode" that is not shared with the other panes. They are available with the right mouse click popup window as well as under the tool's main menu, under the "Display Options" menu pick. * The bp command now outputs a list of existing C breakpoints with their enabled/disabled states in the bp command syntax, so that this output can be saved and executed later to recreate the breakpoints. * The effect of assertions on some coverage features has changed. Because asserion pass counts were not reliable without -assertdebug used in simulation, pass counts have been removed from the coverage database and reports by default. (With -assertdebug, they remain, along with other counts.) Also, the contribution of assertions to total coverage -- in the Verification Management Tracker and Browser -- has changed. Previously, an assertion contributed to "100% coverage" if it non-vacuously passed at least once. Now, with -assertdebug, "100% coverage" is met if an assertion both non-vacuously passed and never failed. Without -assertdebug, "100% coverage" is met if the assertion never failed. There is a new VM Browser column called "%SuccessAsserts" to indicate this statistic. If assertions are included in a test plan, this statistic is automatically used in the VM Tracker and "coverage analyze" command. * Following modifications have been done to coverage switches: Earlier name New name -coverNoSub -nocoversub -nocoverNoSub -coversub -coverExcludeDefault -coverexcludedefault -nocoverExcludeDefault -nocoverexcludedefault -fsmnoresettrans -nofsmresttrans * Errors involving unpacked array assignment, where the packed elements do not match exactly (signed/unsigned, different widths, 2-state/4-state), may now be suppressed using '-suppress 7034'. ______________________________________________________________________ New Features Added to 6.4a * New +cover option for enabling code coverage A new option, +cover, has been added to vlog, vcom, and vopt. This option provides a more flexible use model for enabling code coverage than the currently supported -cover option. The +cover option accepts the same letter codes accepted by the existing -cover option (bcesftx). If no letter codes are given to +cover, then the result is that codes "bcesft" are all activated. This is similar to +acc's behavior with no codes specified. Unlike -cover, the +cover option does not accept a coverOpt number code. Rather, a new option called -coveropt is used to specify a coverOpt number code (more on this option below). When used with vopt, a modifier can be given that matches the behavior of the used with the +acc option. Multiple +cover options can be specified on the same vopt command line. For example: vlog -f filelist.f vopt top -o opttop +cover=bf+/top/dut/core. +cover=s+/top/dut. The above command recursively applies statement coverage to the hierarchy underneath scope "/top/dut". In addition, branch and fsm coverage are applied to the hierarchy underneath scope "/top/dut/core". See the product documentation for more details on the modifier. When +cover is used with vlog and vcom, it works much the same way that -cover works: All design units compiled by the current vlog/vcom session will have the specified coverage flags applied to them. The modifier is not available with +cover when used with vlog or vcom. Various Notes on the new +cover use model: 1. In case +cover is used with both vlog/vcom and vopt, and different letter codes are applied to the same instances or design units, the resulting coverage will be the union of all specified letter codes. 2. In case a -coveropt option specified at vlog/vcom time conflicts with the -coveropt option specified to vopt, the vlog/vcom value has higher priority. 3. The new -coveropt option has higher priority than the old-style -cover . 4. In case +cover=t and +cover=x are active simultaneously on the same instance or design unit, +cover=x prevails, since it is a superset of +cover=t. 5. The interaction between -coveropt and the modelsim.ini "CoverOpt" variable remains the same as with -cover : the command line option has higher priority than the modelsim.ini option. It is recommended that all users migrate to the new +cover code coverage activation model. * HTML coverage report now displays user-defined testplan attributes: (a) in a list at the bottom of each testplan scope summary page, and (b) in a single spreadsheet-like table for the entire testplan. * The simulator is now integrated with Transaction Level Modeling (TLM) Library, Release 2.0 Kit Of 9 June 2008. * The warning message "Connection width does not match width of port" generated by vopt now has a message id number and can be suppressed with the option -suppress 2241. * Code coverage pragmas have been enhanced to selectively turn coverage off and on for specific statements and branches in a line of source code, based on their statement/branch numbers. The -item option has been introduced in code coverage pragmas to facilitate this support. * vlog now reports mismatched `else directives when using the -pedanticerrors switch. * A new preference has been added to control if the Windows keyboard shortcuts for cut/copy/paste are used on Unix platforms. The preference is located in the "By Name" area under Main/PCEditBindingsOnUnix. The default behavior is to _NOT_ use the Windows shortcuts. Note, any opened text windows at the time the preference is changed won't see the change until the next time the GUI is started. * Full support of SystemVerilog DPI open array is available now. Refer to IEEE std 1800-2005 (Annex I.12) for details. * The following FSM related switches have been added: + -fsmresettrans Enable recognition of implicit asynchronous reset transitions for FSMs. + -fsmsingle Enable recognition of FSMs having single bit current state variable. + -nofsmsingle Disable recognition of FSMs having single bit current state variable. + -fsmimplicittrans Enable recognition of implicit transitions in FSMs. + -nofsmxassign Disable recognition of FSMs containing x assignment. * Assertion instances can now be filtered in the GUI browser by their type, concurrent or immediate. This is accessible via the "Display Options" menu.