You can use the Assignment Editor to make assignments in the Quartus® II design software and to edit project defaults and compiler settings.
To add timing assignments or requirements in the Quartus II software, click Timing Wizard… on the Assignments menu (shown in Figure 1). Figure 2 shows the Timing Wizard dialog box.
Figure 1. Menu Selection to Get to Timing Wizard
Figure 2. Timing Wizard
The maximum clock frequency that you can achieve without violating internal setup (tSU) and hold (tH ) time requirements is called fMAX. Using the Timing Wizard, you can specify an overall fMAX requirement for all clocks in the design or define settings that can be applied to individual clocks. Settings defined for an individual clock can be applied to one or more other clocks in the design using the Assignment Editor.
You can also make timing assignments using the Assignment Editor (on the Assignments menu, click Assignment Editor, or use the keyboard shortcut Ctrl+Shift+A). Before editing timing assignments in the Assignment Editor, you must perform a preliminary analysis and elaboration (on the Processing menu, click Start, then click Start Analysis & Elaboration) or a full compilation (on the Processing menu, click Start Compilation ) to generate the design database of entities and nodes.
The Assignment Editor (on the Assignments menu, click Assignment Editor , or use the keyboard shortcut Ctrl+Shift+A) is used to edit project defaults and compiler settings or to make specific entity or node settings. Figure 3 shows the Assignment Editor.
Figure 3. Assignment Editor
An entity is any primitive or macrofunction that can be represented as either a name or a symbol in a design file. A node represents a wire carrying a signal that travels between different logical components of a design file.
Some general examples of global assignments that can be made in the Assignment Editor include:
- Specifying global maximum operating frequency requirements (fMAX)
- Specifying what paths should not be reported in timing analysis reports
- Specifying the number of paths to report in timing analysis reports
- Adding global I/O timing requirements (external input delay, external output delay, minimum delay requirement, tCO, tH, tPD, tSU)
- Selecting logic optimization and mapping options
Before editing specific entity or node settings, you must perform a preliminary analysis and elaboration (on the Processing menu, click Analysis & Elaboration) or a full compilation (on the Processing menu, click Start Compilation) to generate the design database of entities and nodes. You can edit entity or node settings by specifying the entity or node name in the Edit bar of the Assignment Editor or search for an entity or node name using the Node Finder search tool (on the View menu, click Utility Windows, then click Node Finder).
Some general examples of Assignment Editor assignments to specific entity or nodes are:
- Assigning the node or entity to specific locations on the device (e.g., pin, logic array block (LAB), memory, custom-defined region)
- Specifying timing assignments including clock settings, multicycle assignments, I/O timing
- Specifying I/O standard settings
- Specifying routing resource usage settings