Simulation is critical in verifying your design behavior. Simulation of designs written in HDL using a simulator and testbench is a proven technique to verify large designs. The Quartus® II design suite includes the Quartus II simulator and support for all the popular third-party simulators for functional and timing simulations.
Formal verification is a proven way to verify a design's implementation. Quartus II software supports popular third-party industry tools for formal verification.
For additional information on simulation, see the following:
- Simulation Documentation Resources
- Simulation Training and Demonstrations
- Simulation Troubleshooters
- Simulation Design Examples
For additional information on formal verification, see the following:
For a brief overview of the verification and simulation features of the Quartus II software, refer to the Verification and Simulation product feature page.
To search for known simulation and verification issues and technical support solutions, use Altera's Knowledge Database. You can also visit the Altera® Forum to connect and discuss technical issues with other Altera users.
For further technical support, use mySupport to create, view, and update service requests.
Table 1 provides links to available documentation for simulation.
|Table 1. Simulation Support Documentation|
|Quartus II Simulator (PDF)||This detailed chapter in the Quartus II Development Software Handbook explains Quartus II simulator features and simulation flows for functional and timing simulation.|
|These comprehensive chapters from the Quartus II Development Software Handbook provide step-by-step instructions for performing functional register transfer level (RTL), functional post-synthesis, and post-fitting timing simulations with the Mentor Graphics ModelSim/ModelSim-Altera, Synopsys VCS, and Cadence NC-Sim simulation tools.|
|Altera Software Installation and Licensing (PDF)||This chapter describes the requirements and procedures for installing Quartus II software and related software on the Windows and Linux platforms.|
|Simulating Altera IP in Third-Party Simulation Tools (PDF)||Altera intellectual property (IP) provides a quick way to build your design without spending time on writing your own RTL for different components of the design. All Altera IP supports simulation in VHDL and Verilog. This chapter explains how to perform functional and gate-level simulation of Altera IP with third-party simulation tools.|
|AN 351: Simulating Nios II Embedded Processor Designs (PDF)||This application note describes the process of setting up and running an RTL simulation in the ModelSim simulator using Nios® II design examples, SOPC Builder, and the Nios II integrated development environment (IDE).|
|Aldec Active-HDL Support (PDF)||This comprehensive chapter from the Quartus II Development Software Handbook provide step-by-step instructions for performing functional register transfer level (RTL), functional post-synthesis, and post-fitting timing simulations with the Aldec Active-HDL simulation tool.|
|ModelSim Command Reference (PDF)||This command reference manual, developed by Mentor Graphics, describes all ModelSim commands.|
|ModelSim Tutorial (PDF)||This tutorial, developed by Mentor Graphics, provides lessons on using the ModelSim simulator.|
|Table 2. Simulation Demonstrations and Training Courses|
|ModelSim Online Demonstration||
The ModelSim online video demonstration provides a quick overview of using the ModelSim-Altera simulator with the Quartus II software.
This is a 3-minute demonstration.
|Overview of Mentor Graphic's ModelSim Software
The training provides an overview of Mentor Graphic's ModelSim Software.
This is a 1-hour online course.
Using the Quartus II Software: Simulation
Chinese Version: Using the Quartus II Software: Simulation
This online course teaches you how to use the Quartus II simulator to perform functional and timing simulation.
The Quartus II Software Design Series: Verification (Instructor-Led)
This class teaches you how to perform design verification with ModelSim-Altera simulator, PowerPlay power analyzer and debugging tools such as the SignalTap® II embedded logic analyzer, the Logic Analyzer Interface, and the correct tools to effectively debug your design.
This is an 8-hour instructor-led course.
Formal Verification Resources
Table 3 provides links to available documentation for formal verification.
|Table 3. Formal Verification Resources|
|Cadence Encounter Conformal Support (PDF)
Synopsys Formality Support (PDF)
|These comprehensive chapters in the Quartus II Development Software Handbook provide step-by-step instructions for performing formal verification with third-party tools from Cadence and Synopsys.|