The Qsys system integration tool in Quartus® II software saves time and effort in the FPGA design process by enabling faster system development and design reuse. Qsys automatically generates interconnect logic to connect intellectual property (IP) functions and subsystems. Qsys replaces the SOPC Builder tool for new designs.
For an overview of Qsys features, refer to the Qsys product page.
Qsys Documentation
Interface Standard Specifications
Verification IP and Bus Functional Models (BFMs) |
Tutorials and Training
Designs and IP Migration Guidelines and Known Issues |
