SOPC Builder Component Development Flow Using the Component Editor Overview
The component editor packages components for SOPC Builder. The created components are usually based on the Verilog HDL or VHDL that can be easily reused in other systems. You can also build non-HDL-based components that export the Avalon® system interconnect signals to the top level of your SOPC Builder system to connect to external logic or devices.
If you have a component design or external device that does not have Avalon compatible signals, you can always build an Avalon interface for your component from HDL files and export the control signals to your component or external device with conduits using the HDL-based component flow. This will allow you to easily interface to any non-HDL-based designs (such as schematic files) with your SOPC Builder system without changing the original design files. This same methodology can be used to build a custom interface to any external device that can interface with your SOPC Builder system through exported signals.
There are two flows to build your component in component editor: HDL and non-HDL-based flow. Most components are built using the HDL-based flow.
The following component development flows use the SOPC Builder component editor version 7.2 or later to construct the support files that describe the component in SOPC Builder.
HDL-Based Component Flow in the Component Editor
You can use the HDL-based component development flow in the component editor if you have built your component from Verilog HDL or VHDL files that have Avalon Memory Mapped or Avalon Streaming compatible signals:
- Start the component editor from SOPC Builder by selecting New Component from the File pull down menu or clicking Create New Component… from the SOPC Builder system content list
- Click on the HDL Files tab and click Add HDL File
- The top-level HDL file must be the first file in the list.
- Select the top-level module of your component from the pull down menu.
- Add your HDL and Simulation support files to the Simulation Files list for functional HDL simulation support
- Click on the Signals tab and assign Avalon interfaces and signal types to all component signals.
- You can assign or create new interfaces for your signals by selecting a signal and using the pull down menu in the Interface column. New interfaces are given a default name that can be changed in the Interfaces tab
- Click on the Interfaces tab to configure each interface
- Each interface should be associated with a clock interface to synchronize the Avalon interface signals to the Avalon port
- Remove the default or unused interfaces by clicking Remove Interfaces With No Signals if it is enabled
- Click on the Component Wizard tab to configure the component description and assign the component to a component group
Non-HDL-Based Component Flow in the Component Editor
You can use the non-HDL-based flow to export the Avalon interface signals to the top level of your system if you have a component not built with HDL files or an external device with Avalon compatible signals. The exported Avalon interface signals can then be connected to your component design files with from the top-level design file.
- Skip the HDL Files tab
- Click on the Signals tab and add signals for your non-HDL-based component
- The Templates menu can be used as a starting point for each Avalon port
- Use the Add Signal button to add signals and configure them by assigning a name, the Avalon interface, signal type, width, and direction
- You can assign or create new interfaces for your signals by selecting a signal and using the pull down menu in the Interface column. New interfaces are given a default name that can be changed in the Interfaces tab
- Click on the Interfaces tab to configure each interface
- Each interface should be associated with a clock interface to synchronize the Avalon Interface signal to the Avalon port
- Remove the default and unused interfaces by clicking Remove Interfaces With No Signals if it is enabled
- Click on the Component Wizard tab to configure the component description and assign the component to a component group
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