DSP Builder (consisting of an advanced and standard blockset) allows for high-performance push-button hardware description language (HDL) generation of digital signal processing (DSP) algorithms directly from the Simulink environment. Altera recommends using the advanced blockset for new designs as it allows algorithm designers to:
- Go from high-level schematic into low-level optimized VHDL targeted for your Altera® FPGAs including the latest 28 nm (Stratix® V, Arria® V, and Cyclone® V FPGAs) offerings
- Perform high-performance fixed and floating-point DSP with vector processing (such as complex IEEE-754 single-precision floating-point). Read the BDTI benchmark white paper on the Floating-Point DSP Solutions page
- Use a designer-specified system clock constraint to automatically pipeline, time-division multiplex/fold, and close timing
- Access advanced Math.h functions and multi-channel data
- Generate resource utilization tables for all designs without a Quartus® II software compile
- Automatically generate projects or scripts for Quartus II software, TimeQuest, Qsys, and ModelSim®-Altera software
What MathWorks tools are required for DSP Builder Advanced Blockset? (Sold seperately here)
- MATLAB (required)
- Simulink (required)
- Simulink Fixed-Point and Fixed-Point Toolbox (required)
- Signal Processing Toolbox (recommended)
Figure 1. DSP Builder Tool Flow
Figure 2. DSP Builder Advanced Blockset
What are the design examples that come with DSP Builder?
- Interpolating/decimating cascaded integrator comb (CIC), finite impulse response (FIR), and multichannel infinite impulse response (IIR) filters
- 1K, 4K, 8K point fast Fourier transform (FFT) and inverse FFT (IFFT)
- Cholesky or QR-based matrix solvers
- Digital up/down conversion
- Complex mixer
- Beamforming
- Black-Scholes algorithm
- Field-oriented motor control (FOC)
- Mandlebrot set
DSP Builder Floating-Point Capabilities
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See how 28 nm FPGAs can perform at one teraFLOPS. Read white paper (PDF) |
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Learn how Altera FPGAs solve floating-point challenges. View webcast |
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See how BDTI, an independent technology analysis firm, evaluates the energy efficiency of Altera's floating-point DSP on 28 nm development kits. |
Updates in Quartus II Software v12.1
- Improved design productivity with extended math.h primitive block coverage and support for seven different floating-point precisions, including IEEE-754 half, single, and double precisions
- Improved design reuse with new multifunction blocks that allow parameterized math functions
- Improved FFT implementation with improved radix-2^2 blockset (parameterized top-level FFT block and inverse FFT support)
Get DSP training today! Register for either the online one-hour training or attend one of our in-person training sessions to learn more about the DSP Builder Advanced Blockset .
Note about DSP Builder Standard Blockset:
Altera continues to support DSP Builder Standard Blockset. Both standard and advanced blockset functionality can be implemented at different Simulink hierarchy levels within a design.
DSP Documents
- An Independent Analysis of Floating-Point DSP Design Flow and Performance on Altera 28 nm FPGAs (PDF)
- DSP Builder Advanced Blockset User Guide (PDF)
- DSP Builder Advanced Blockset Reference Manual (PDF)
- DSP Builder Release Notes and Errata (PDF)
- DSP documentation
